Data processing system and method of operation having input/outp

Details Data processing system and method of operation having input/outp Data processing system and method of operation having input/outp

1996-09-18

1999-10-26

Lim, Krisna

395555, G06F 100, G06F 104

Patent

active

059742593

ABSTRACT:
A data processing system has a memory bus and a system input/output (I/O) bus including I/O drivers. The memory and I/O buses are controlled by a central processor unit (CPU) for transferring data therebetween and to the I/O drivers. A central clock provides clock signals to the CPU, the memory bus and the I/O bus. The central clock further provides memory and I/O phase alignment signals to the CPU, the alignment signals indicating to the CPU when the start of the CPU clock cycle coincides with the start of a memory bus clock cycle or I/O bus clock signal. Circuit means responsive to the phase alignment and CPU clock signals initiate the transfer of data to the memory and I/O data buses in alternate CPU clock signals to reduce the number of I/O pin switching at any given time thereby reducing the noise and power consumption at the I/O pins and in the system.

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