Data processing system and method for testing a data processor h

Details Data processing system and method for testing a data processor h Data processing system and method for testing a data processor h

1994-01-28

1996-12-17

Kim, Matthew M.

3954211, 39542103, 395455, G06F 1208

Patent

active

055862799

ABSTRACT:
A cached processor (2) comprises a cache memory (8') having mode switching means for selecting an address capture mode whereby information, such as data and/or instructions, can be captured and stored in all or part of a cache array (30) of the cache memory in real time. The captured information can at any time be transferred to, and used by, an external debug station, coupled to the cached processor, to observe the executed program flow.

REFERENCES:
patent: 4811209 (1989-03-01), Rubinstein
patent: 5014195 (1991-05-01), Farrell et al.
patent: 5113506 (1992-05-01), Moussouris et al.
patent: 5210843 (1993-05-01), Ayers
patent: 5287481 (1994-02-01), Lin
patent: 5287490 (1994-02-01), Sites
patent: 5301296 (1994-04-01), Mohri et al.
patent: 5317718 (1994-05-01), Jouppi
patent: 5367660 (1994-11-01), Gat et al.
patent: 5386547 (1995-01-01), Jouppi
patent: 5418922 (1995-05-01), Liu

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