Data processing system and method for controlling the latter as

Details Data processing system and method for controlling the latter as Data processing system and method for controlling the latter as

1993-02-17

1994-04-26

Fleming, Michael R.

Boots, shoes, and leggings

395425, 36424291, 3642423, 364DIG1, G06F 1314

Patent

active

053074688

ABSTRACT:
A method and apparatus for controlling accesses to main memory by a CPU includes a CPU coupled to the main memory by a first switching device. A system bus is coupled to main memory by a second switching device. The system bus couples a plurality of functional units to main memory. The first and second switching devices are interconnected so that only one of the two switching mechanisms can release the connection between the CPU or the system bus and the main memory. Advantageously, a first buffer is coupled between the main memory and the CPU for temporary storage of data which is to be transferred between the CPU and main memory, and a second buffer is coupled between main memory and the system bus for temporary storage of data which is to be transferred between the system bus and main memory. The main memory, the first and second switching mechanisms as well as the first and second buffers are provided on the same board as the CPU.

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Halang, Wolfgang A. Microprocessing and Microprogramming, "On Methods for Direct Memory Access Without Cycle Stealing", Amsterdam, Netherlands, May 1986.

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