Computer graphics processing and selective visual display system – Computer graphic processing system – Integrated circuit
Reexamination Certificate
2000-05-30
2001-09-11
Tung, Kee M. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphic processing system
Integrated circuit
C345S534000
Reexamination Certificate
active
06288728
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a data processing system and an image processing system in the field of an information terminal such as a personal computer or a workstation for processing the image data allocated on a memory and, more particularly, to a technique which is effective when applied to a high-speed image processing system for accessing a memory at a high speed in synchronism with a clock.
In the image processing system, a drawing display processor executes a drawing processing upon a frame buffer in accordance with drawing commands or parameters transferred from a CPU. This drawing display processor may execute the drawing processing in accordance with the drawing commands or parameters which are arranged in advance in the frame buffer or a special purpose local memory. Moreover, the drawing display processor reads out the necessary display data from the frame buffer in accordance with the horizontal and vertical synchronizing timings and the dot rate of the monitor and displays them on the monitor through a dot shifter. The clock generator produces a fundamental clock and a dot clock on the basis of the reference frequency of a quartz oscillator and feeds them to the drawing display processor and the dot shifter. As the frame buffer of such image processing system, there can be adopted a DRAM (i.e., Dynamic Random Access Memory) or a multi-port DRAM which is given such a large storage capacity as is required for the bit map arrangement of the display data.
In the image processing system used in a facsimile, a printer or a graphic device of the prior art, on the other hand, there are used a high-speed SRAM (i.e., Static Random Access Memory) as a local processing referring to peripheral pixels, as disclosed in Japanese Patent Laid-Open No. 261969/1986, and a DRAM as a large-capacity memory for storing code data and font data.
SUMMARY OF THE INVENTION
In the trends of the field of the information terminal device of recent years such as a personal computer or workstation for business uses, the high quality, operation speed and capacity are advanced to increase the data bus width in case the frame buffer is constructed of a standard DRAM. In other constructions adopted, the drawing processing efficiency is improved by constructing the frame buffer of the multi port DRAM. In accordance with this, there arises a problem that the cost for the system rises.
On the other hand, the synchronous DRAM has been noted as a large-capacity memory. This synchronous DRAM can input/output data, addresses and control signals in synchronism with clocks, as different from the DRAM-of the prior art, so that it can realize a large-capacity memory equivalent to the DRAM at a speed as high as that of the SRAM. Thus, the synchronous DRAM can achieve a higher speed access and a larger capacity more than those of the DRAM of the prior art at a reasonable cost. This synchronous DRAM can designate how many data are to be accessed for one selected word line, in terms of a bust length, for example. In case the burst length is N, an N number of data can be sequentially read or written by switching the selected states of a column line by an internal column address counter. Incidentally, the application of the synchronous DRAM to a main memory or for graphics is disclosed, for example, in the electronic technology on pp. 24 to 28 (1993) of “Applications to Main Memory or Graphics of High-Speed DRAM”.
We have examined an image processing system which is enabled to access a large-capacity a high-speed memory at a low cost by integrating a high-speed processing memory and a large-capacity memory. Specifically, we have examined the case in which a system is to be constructed by using the synchronous DRAM as a memory having a function to latch addresses, data and control signals in synchronism with clocks, and have come to the conclusions discussed below.
Firstly, in order to realize a high-speed access while holding the reliability of an accessing operation, the skews between the data, addresses and control signals outputted by the circuit modules and the clock signals are required to have a small value by the characteristics of the synchronous DRAM for inputting/outputting the data, addresses and control signals in synchronism with the clocks.
Secondly, when drawing a straight line in an arbitrary direction, the memory addresses are not continuous in the same row address so that the burst length is desired to have a value 1. In a rectangular smearing drawing for clearing the memory, on the other hand, the memory addresses are continuous in the same row address so that the burst length is desired to have a value N (N>1). Thus, the processing of changing the burst length in accordance with the drawing processing content is desired to be executed in the display control system.
Thirdly, there is further examined the case in which the synchronous DRAM is used to construct the system. Thanks to the use of the synchronous DRAM, a clock timing for outputting the read data, for example, can be designated after an address to be accessed has been issued, so that a next address can be issued before the read processing has been completed. In case the addresses are to be subsequently issued, they are limited to belong to the same row address. In order to access the different row addresses in the same bank, therefore, there is required a mishit processing such as a precharge processing.
An object of the present invention is to provide a technique for solving the several problems, which are caused when a clock-synchronized type memory having a high-speed operation and a large capacity such as the synchronous DRAM is to be applied to an image processing system, and for realizing an inexpensive, high-performance image processing system and a data processing system, and a data processor for the systems.
More specifically, an object of the present invention is achieved such, a processing for changing the burst length according to a processing content which occur when a system having an integrated memory is to be constructed by using the synchronous DRAM. Another object is to improve the bus throughput of the memory at a low cost in accordance with the burst length. A further object is to realize the mishit processing at a low cost and at a high speed. A further object is to provide a data processor optimized for controlling the access of a clock-synchronized type memory such as the synchronous DRAM having a high-speed operation and a large capacity.
The foregoing and other objects and novel features of the present invention will become apparent from the following description to be made with reference to the accompanying drawings.
Representatives of the invention to be disclosed herein will be briefly described in the following. Specifically, the present invention is coarsely divided into the feed of clock signals to a memory such as the synchronous DRAM, the setting of a mode register for designating the operation modes, and the processing of a mishit.
Feed of Clocks
A data processor comprises: bus control means (
14
) interfaced with a memory (
22
) such as a synchronous DRAM for inputting addresses, inputting/outputting data and inputting control signals in synchronism with a clock signal (CLK) fed from the outside; a plurality of data processing modules (
12
,
13
) coupled to said bus control means for individually producing data and addresses to access said memory; and clock feed means for feeding said data processing modules with individually intrinsic operation clock signals and for feeding the clock signals for accessing said memory to the outside in synchronism with the operations of said data processing modules actuated by an intrinsic operation clock fed.
In order that the data processor may be easily applied to the case in which the plurality of data processing modules have different operation speeds, said clock feed means includes: a plurality of clock drivers (
16
c
,
16
s
) disposed for the individual operation speeds of said plurality of data processing modules; and a clock
Katsura Koyo
Miyamoto Takashi
Nakashima Keisuke
Ohmura Kenichiroh
Satoh Jun
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
Tung Kee M.
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