Patent
1993-11-01
1997-06-10
Chan, Eddie P.
395496, 39542108, 39542109, G06F 1202
Patent
active
056385285
ABSTRACT:
A method and apparatus for controlling a bus within a data processing system has a first control bit (SAS*), and second control bit (CLA*), and at least one termination signal (TA*, TRA*, TEA*). The CLA* signal is an input to a primary master (10). The primary master (10) provides a base address external to the primary master (10) so that a slave device can access the base address. The CLA* signal is asserted by the slave device to signal that the base address is to be cycled in a bit-wise circular fashion to provide a plurality of addresses out from the primary master (10) wherein each address in the plurality is derived from the base address internal to the primary master (10). Typically four addresses are provided per base address via the internal control of the primary master (10) in response to three sequential assertions of the CLA* signal.
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Gay James G.
Gokingco Jefferson L.
Hansen John P.
Stence Ronald W.
Chan Eddie P.
Motorola Inc.
Nguyen Hiep T.
Witek Keith E.
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