Boots – shoes – and leggings
Patent
1980-04-25
1983-05-31
Ruggiero, Joseph F.
Boots, shoes, and leggings
G06F 936
Patent
active
043863990
ABSTRACT:
A data processing system which handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded. The decoded macro-instructions provide the starting address of one or more micro-instructions, which address is supplied to a unique micro-instruction sequencing unit which appropriately decodes a selected field of each micro-instruction to obtain each successive micro-instruction. The system uses hierarchical memory storage using eight storage segments (rings), access to the rings being controlled in a privileged manner according to different levels of privilege. The memory system uses a bank of main memory modules which interface with the central processor system via a dual port cache memory, block data transfers between the main memory and the cache memory being controlled by a bank controller unit.
REFERENCES:
patent: 3934232 (1976-01-01), Curley et al.
patent: 4050058 (1977-09-01), Garlic
patent: 4051461 (1977-09-01), Hashimoto et al.
patent: 4160289 (1979-07-01), Bambara et al.
Alsing Carl J.
Coyle Richard W.
Druke Michael B.
Guyer James M.
Holberger Kenneth D.
Data General Corporation
Fleming Michael R.
O'Connell Robert F.
Ruggiero Joseph F.
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