Data processing system

Boots – shoes – and leggings

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G06F 752

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active

045890862

ABSTRACT:
A data processing system having an arithmetic unit is designed for a multiplication of n-place numbers in 2's complement according to the Booth algorithm, and for division of unsigned numerals. A 2n-stage shift register is connected over a logical control circuit to the operation code inputs of an ALU. The control circuit automatically forms instruction code signals to the ALU as a function of informational bits derived from the shift register, whereas other operation code input signals are directly connected to the operation code inputs. The control circuit is a sequential circuit having a multiplexer for the selective through-connection of the multiplication code signals, the division code signals, or other operation code signals to the operation code inputs of the ALU.

REFERENCES:
patent: 3631230 (1971-12-01), Chen
patent: 4228518 (1980-10-01), Chamberlin
patent: 4238833 (1980-12-01), Ghest
patent: 4484259 (1984-11-01), Palmer et al.
Mori et al., "A Special-Purpose Computer for Digital Signal Processing" IEEE Trans. on Computers, vol. C-24 #12, Dec. 1975, pp. 1202-1211.
Louis Schirm IV "Digital Signal Processing Systems Move to Floating Point Arithmetic Part 2: Implement 32 Bit Mulitplication Computer Design, vol. 19, #9, 9/80, pp. 188-193.
Shlomo Waser "High Speed Monolithic Multipliers for Real-Time Digital Signal Processing" Computer Oct. 1978 pp. 19-29.

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