Data processing method and apparatus operable on an irrational m

Details Data processing method and apparatus operable on an irrational m Data processing method and apparatus operable on an irrational m

1998-03-25

2000-08-08

Malzahn, David H.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

708204, 708605, G06F 758

Patent

active

061015210

ABSTRACT:
A data processing apparatus (200) which improves the accuracy of resultant data. The data processing apparatus includes an input (220, 222) configured to receive input data. The input data includes data corresponding to an input coefficient to be multiplied by the square root of two (.sqroot.2) and input addend. The data processing apparatus further includes a first memory (202) for storing a coefficient of the square root of two, a second memory (204) for storing an addend, a summer (206, 208) which independently sums the input coefficient and the coefficient to produce a combined coefficient and sums the input addend and the addend to produce an addend sum, a multiplier (210) which multiplies the combined coefficient and an approximation of the square root of two to produce an intermediate result, and a summer (214) which sums the intermediate result and the addend sum to produce the resultant data.

REFERENCES:
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patent: 5608663 (1997-03-01), Smith
patent: 5619711 (1997-04-01), Anderson
patent: 5948048 (1999-09-01), Kim
Schreier et al., "Decimation for Bandpass Sigma-Delta Analog-to-Digital Conversion", IEEE, 1990, pp. 1801-1804.

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