Data processing method and apparatus including iterative multipl

Details Data processing method and apparatus including iterative multipl Data processing method and apparatus including iterative multipl

1994-08-26

1996-09-17

Mai, Tan V.

Boots, shoes, and leggings

364736, G06F 752, G06F 738

Patent

active

055575633

ABSTRACT:
An iterative multiplier having a multiplier core generating partial results upon each iteration. When an early terminate of a multiply instruction occurs, at least one of the partial results is passed to a general purpose barrel shifter for bit realignment dependent upon the number of iterations performed before the early terminate occurred. The bit realigned partial results are then passed to an arithmetic logic unit where they are added to yield the final result.

REFERENCES:
patent: 4868777 (1989-09-01), Nishiyama et al.
patent: 5126963 (1992-06-01), Fukasawa

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