Data processing method and apparatus having plural bus interface

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364243, 364244, 3642443, 3642446, 3642384, 3642328, G06F 300

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049791036

ABSTRACT:
A method and apparatus for controlling a plurality of bus interfaces in a system including on one chip a central processing unit and an internal memory. A first operand retrieving operation is executed by a first operand retrieving unit when one operand is discriminated that is located outside a chip, and a second operand retrieving operation is executed by a second operand retrieving unit when another operand is discriminated that is located inside the chip, so that the operand is read to the central processing unit in accordance with the bus interface signals of the first and the second operand retrieving units.

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"Microprocessors", IEEE Spectrum, Jan. 1985, pp. 53-55.

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