Data processing device with test control circuit

Details Data processing device with test control circuit Data processing device with test control circuit

1991-04-29

1994-11-08

Nguyen, Hoa T.

Excavating

395575, G06F 1100

Patent

active

053633806

ABSTRACT:
Disclosed is a data processing device with a test control circuit comprising a CPU, peripheral devices such as a ROM, a RAM, and the like, an address bus through which the CPU is connected to the peripheral devices, an input/output circuit as an interface circuit for controlling transfer of data input/output and an address signal between the address bus and the data bus and an external device, and a control circuit incorporated in the data processing device for isolating the address bus and the data bus from the CPU in a test mode of the device and for controlling the input/output operations for the peripheral devices, the operation of the input/output control circuit, and the operation of the CPU.

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Design for Testability for Microprocessor-Based Boards, R. Willis, Electronic Engineering Apr. 1983, vol. 56, No. 676, pp. 67, 68, 69, 72.

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