Data processing device with test circuit

Details Data processing device with test circuit Data processing device with test circuit

1994-12-14

1996-05-07

Auve, Glenn A.

Excavating

395311, 371 221, G06F 1126

Patent

active

055155170

ABSTRACT:
A data processing device with a test circuit has a plurality of macro blocks, a common bus for transferring the output of one of the macro blocks to the other macro blocks, and a tri-state buffer incorporated into each macro block. A bus control circuit selects the tri-state buffer in a normal operation mode in which the device performs its normal functions, in order to transfer the information stored in the macro block corresponding to the tri-state buffer selected by the bus control circuit to the common bus. A selecting control circuit, which includes a selector, an AND gate, and a flip-flop (F/F), is used for selecting the tri-state buffer in a test operation mode which the device has entered, then for transferring the information stored in the macro block corresponding to the tri-state buffer selected by the selecting control circuit to the common bus. A F/F is provided for setting the device in either the normal operation mode or the test operation mode. In the data processing device according to the present invention, in addition to the bus control circuit, which is used in the normal operation mode, the selecting control circuit, which is used in the test operation mode, is provided, so that the efficiency of the test vector generation is greatly improved.

REFERENCES:
patent: 4495573 (1985-01-01), Ballegeer et al.
patent: 4511958 (1985-04-01), Funk
patent: 4535330 (1985-08-01), Carey et al.
patent: 4825439 (1989-04-01), Sakashita et al.
patent: 4910735 (1990-03-01), Yamashita
patent: 4973904 (1990-11-01), Sonnek
patent: 4980889 (1990-12-01), DeGuise et al.
patent: 4984195 (1991-01-01), Nakamura et al.
patent: 4987529 (1991-01-01), Craft et al.
patent: 5019970 (1991-05-01), Yamaguchi et al.
patent: 5034881 (1991-07-01), Hoashi et al.
patent: 5101498 (1992-03-01), Ehlig et al.
patent: 5115435 (1992-05-01), Langford, II et al.
patent: 5157781 (1992-10-01), Harwood et al.
patent: 5159263 (1992-10-01), Yaguchi
patent: 5210864 (1993-05-01), Yoshida et al.
patent: 5247521 (1993-09-01), Akao et al.
patent: 5331571 (1994-07-01), Aronoff et al.
Testability Features of the MC68332 Modular Microcontroller, W. Harwood et al., Proceedings of the International Test Conference, Aug. 29-31, 1989, pp. 615-623, New York, U.S.
System-und Software-Architektur des Multibus-II, F. Furrer, Elektronik, vol. 37, No. 21, Oct. 1988, pp. 78-84, Munchen de (an English abstract is attached to this document).
A Universal Test and Maintenance Controller for Modules and Boards, J-C Lien et al., IEEE Transactions On Industrial Electronics and Control Instrumentation, vol. 36, No. 2, May 1989, New York, U.S., pp. 231-240.

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