Data processing device with processors arranged in a looped line

Details Data processing device with processors arranged in a looped line Data processing device with processors arranged in a looped line

1988-11-15

1991-09-10

Razavi, Michael

Image analysis

Histogram processing

For setting a threshold

382 27, 358489, 3642293, G06K 900

Patent

active

050481088

ABSTRACT:
The present invention concerns a data-processing device relating to pixels. This data is marked per line and per column. The device comprises processing means comprising at least four identical processors, (PE0, PE1, PE2, PE3) respectively connected to memories (MEM0, MEM1, MEM2, MEM3) marked on row J=0 to row J=3. The data relating to the pixels to be processed are recorded in the memories according to an helicoidal addressing. Connection means (1C0, 1C1, . . . , 2C0, 2CE1, . . . ) are provided so that the processors are connected according to a looped line configuration.

REFERENCES:
patent: 3814906 (1974-06-01), Trotta
patent: 4908751 (1990-03-01), Smith
patent: 4949390 (1990-08-01), Iverson et al.
Conference Proceedings, the 10th International Symposium on Computer Architecture, pp. 395-400.
IEEE 1983 International Symposium on Circuits and Systems, vol. 1, pp. 405-408.

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