Data processing device with multiple on-chip memory buses

Details Data processing device with multiple on-chip memory buses Data processing device with multiple on-chip memory buses

1990-01-02

1992-12-29

Fleming, Michael R.

Boots, shoes, and leggings

364DIG1, 3642402, 364243, G06F 1328

Patent

active

051758415

ABSTRACT:
A microcomputer is disclosed which is specifically designed for computation-intensive applications. The microcomputer contains on-chip RAM and ROM, and has peripheral ports for access of external memory and input/output functions. The microcomputer has a central processing unit with a floating-point multiplier in parallel with an arithmetic logic unit, and uses a plurality of registers as multiple accumulators. The central processing unit further contains two auxilary arithmetic logic units, in parallel with one another, and which are each connected to a set address lines in a memory bus; the two auxiliary arithmetic logic units thus generate two separate memory addresses in parallel. The memory bus also contains one set of data lines, connected to the RAM and ROM, and to the central processing unit. The on-chip RAM and ROM are responsive to the two sets of address lines in time-multiplexed fashion to provide memory access via data lines twice per system clock cycle. A second memory bus is also connected to the on-chip RAM and ROM, and to the peripheral ports, so that access to one of the memory elements via said first memory bus can occur simultaneously with, and independently from, access to another of said memory elements via said second memory bus. The on-chip memory and external memory are all mapped into a single memory address space, which allows simultaneous program and data fetches via the two memory buses, or a program and data fetch during the same cycle using the first time-multiplexed bus. Memory-mapped input and output functions are performed by on-chip peripherals, which are connected to a peripheral bus connected to one of the peripheral ports of the microcomputer. The peripheral bus allows for substantial flexibility relative to the configuration of the microcomputer.

REFERENCES:
patent: 4263649 (1981-04-01), Lapp, Jr.
patent: 4348720 (1982-09-01), Blahut et al.
patent: 4514808 (1985-04-01), Murayama et al.
patent: 4558412 (1985-12-01), Inoshita et al.
patent: 4564900 (1986-01-01), Smith
patent: 4577282 (1986-03-01), Caudel et al.
patent: 4648029 (1987-03-01), Cooper et al.
patent: 4716523 (1987-12-01), Burrus, Jr. et al.
patent: 4912636 (1990-03-01), Magar et al.

Affiliated with

Also associated with

Rating

Data processing device with multiple on-chip memory buses does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data processing device with multiple on-chip memory buses, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data processing device with multiple on-chip memory buses will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1893792