Data processing device with multiple on chip memory buses

Details Data processing device with multiple on chip memory buses Data processing device with multiple on chip memory buses

1987-03-13

1990-03-27

Heckler, Thomas M.

Boots, shoes, and leggings

3642402, 364243, G06F 1328

Patent

active

049126369

ABSTRACT:
A microcomputer is disclosed which is specifically designed for computation-intensive applications. The microcomputer contains on-chip RAM and ROM, and has peripheral ports for access of external memory and input/output functions. The microprocessor has a central processing unit with a floating-point multiplier in parallel with an arithmetic logic unit, and uses a plurality of registers as multiple accumulators. The central processing unit further contains two auxillary arithmetic logic units, in parallel with one another, and which are each connected to a set of address lines in a memory bus; the two auxillary arithmetic logic unit thus generate two separate memory addresses in parallel. The memory bus also contains one set of data lines, connected to the RAM and ROM, and to the central processing unit. The on-chip RAM and ROM are responsive to the two sets of address lines in time-multiplexed fashion to provide memory access via data lines twice per system clock cycle. A second memory bus is also connected to the on-chip RAM and ROM, and to the peripheral ports, so that access to one of the memory elements via said first memory bus can occur simultaneously with, and independently from, access to another of said memory elements via said second memory bus. The on-chip memory and external memory are all mapped into a single memory address space, which allows simultaneous program and data fetches via the two memory buses, or a program and data fetch during the same cycle using the first time-multiplexed bus. Memory-mapped input and output functions are performed by on-chip peripherals, which are connected to a peripheral bus connected to one of the peripheral ports of the microcomputer. The peripheral bus allows for substantial flexibility relative to the configuration of the microcomputer.

REFERENCES:
patent: 3757306 (1973-09-01), Boone
patent: 3810114 (1974-05-01), Yamada et al.
patent: 4074351 (1978-02-01), Boone et al.
patent: 4096567 (1978-06-01), Millard et al.
patent: 4263649 (1981-04-01), Lapp, Jr.
patent: 4310879 (1982-01-01), Pandeya
patent: 4314333 (1982-02-01), Shibayama et al.
patent: 4348720 (1982-09-01), Blahut et al.
patent: 4453215 (1984-06-01), Reid
patent: 4481573 (1984-11-01), Fukunaga et al.
patent: 4514808 (1985-04-01), Murayama et al.
patent: 4527237 (1985-07-01), Frieder et al.
patent: 4542256 (1985-09-01), Hill
patent: 4558412 (1985-12-01), Inoshita et al.
patent: 4564900 (1986-01-01), Smitt
patent: 4577282 (1986-03-01), Caudel et al.
patent: 4620275 (1986-10-01), Wallach et al.
patent: 4627026 (1986-12-01), Di Giugno
patent: 4648029 (1987-03-01), Cooper et al.
patent: 4716523 (1987-12-01), Burrus, Jr. et al.
patent: 4719568 (1988-01-01), Carrubba et al.
patent: 4791590 (1988-12-01), Ku et al.
J. Boddie et al., "Digital Signal Processor: Architecture and Performance", The Bell System Technical Journal, vol. 60, No. 7, Sep. 1981, pp. 1449-1463.
P. Kogge, The Architecture of Pipelined Computers, McGraw-Hill Book Company, pp. 38-47, 1981.
M. Yano et al., "An LSI Digital Signal Processor", IEEE, 1982, pp. 1073-1076.

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