Data processing device with improved direct memory access

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3642402, 3642423, 36424231, 364DIG1, G06F 1328

Patent

active

050994174

ABSTRACT:
A microcomputer is disclosed which is specifically designed for computation-intensive applications. The microcomputer contains on-chip RAM and ROM, and has peripheral ports for access of external memory and input/output functions. The microcomputer has a central processing unit with a floating-point multiplier in parallel with an arithmetic logic unit, and uses a plurality of registers as multiple accumulators. The central processing unit further contains two auxiliary arithmetic logic units, in parallel with one another, and which are each connected to a set address lines in a memory bus; the two auxiliary arithmetic logic units thus generate two separate memory addresses in parallel. The memory bus also contains one set of data lines, connected to the RAM and ROM, and to the central processing unit. The on-chip RAM and ROM are responsive to the two sets of address lines in time-multiplexed fashion to provide memory access via data lines twice per system clock cycle. A second memory bus is also connected to the on-chip RAM and ROM, and to the peripheral ports, so that access to one of the memory elements via said first memory bus can occur simultaneously with, and independently from, access to another of said memory elements via said second memory bus. The on-chip memory and external memory are all mapped into a single memory address space, which allows simultaneous program and data fetches via the two memory buses, or a program and data fetch during the same cycle using the first time-multiplexed bus. Memory-mapped input and output functions are performed by on-chip peripherals, which are connected to a peripheral bus connected to one of the peripheral ports of the microcomputer. The peripheral bus allows for substantial flexibility relative to the configuration of the microcomputer.

REFERENCES:
patent: 3757306 (1973-09-01), Boone
patent: 4074351 (1978-02-01), Boone et al.
patent: 4245301 (1981-01-01), Rokutanda et al.
patent: 4263648 (1981-04-01), Stafford et al.
patent: 4314333 (1982-02-01), Shibayama et al.
patent: 4348720 (1982-09-01), Blahut et al.
patent: 4371926 (1983-02-01), Yamaura et al.
patent: 4424565 (1984-01-01), Larson
patent: 4514808 (1985-04-01), Murayama et al.
patent: 4527237 (1985-07-01), Frieder et al.
patent: 4528626 (1985-07-01), Dean et al.
patent: 4543644 (1985-09-01), Kozima et al.
patent: 4558412 (1985-12-01), Inoshita et al.
patent: 4564900 (1986-01-01), Smitt
patent: 4577282 (1986-03-01), Caudel et al.
patent: 4648029 (1987-03-01), Cooper et al.
patent: 4688166 (1987-08-01), Schneider
patent: 4716523 (1987-12-01), Burrus, Jr. et al.
patent: 4782439 (1988-11-01), Borkar et al.
patent: 4797853 (1989-01-01), Savage et al.
P. Kogge, The Architecture of Pipelined Computers, McGraw-Hill Book Company, pp. 38-47, 1981.
M. Yano et al., "An LSI Digital Signal Processor", IEEE, 1982, pp. 1073-1076.
NEC Electronics U.S.A. Inc., 1982 Catalog, pp. 551-567.
H. Kikuchi et al., "A 23K Gate CMOS DSP with 100ns Muliplication", IEEE International Solid-State Circuits Conference, 1983, pp. 128-129.
R. Kershaw et al., "A Programmable Digital Signal Processor with 32b Floating Point Arithmetic", IEEE International Solid-State Circuits Conference, 1985, pp. 92-93, 318.
Y. Mochida et al., "A High Performance LSI Digital Signal Processor for Communication", IEEE Journal on Selected Areas in Communications, vol. SAC-3, No. 2, 1985, pp. 347-356.
H. Yamauchi et al., "An 18-Bit Floating-Point Signal Processor VLSI with an On-Chip 512W Dual-Port RAM", IEEE, 1985, paper 6.4, pp. 204-207.
W. Hays et al., "A 32-Bit VLSI Digital Signal Processor", IEEE Journal of Solid-State Circuits, vol. SC-20, No. 5, 1985, pp. 998-1004.
Hirohisa Gambe et al., On the Design of a High-Performance LSI Circuit Digital Signal Processor for Communication, IEEE Journal on Selected Areas in Communications, vol. SAC-3, No. 2, Mar. 1985, pp. 357-364.
Takao Kaneko et al., A 50NS Floating-Point Signal Processor VLSI, ICASSP 86, Tokyo, pp. 401-404.
Yoshikazu Mori et al., Architecture of High-Speed 22-Bit Floating-Point Digital Signal Processor, ICASSP 86, Tokyo, pp. 405-408.
DSP56001, Technical Summary, 56-Bit General Purpose Digital Signal Processor, Motorola Semiconductor Technical Data, 1986, pp. 1-13.

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