Electrical computers and digital processing systems: processing – Processing architecture – Long instruction word
Reexamination Certificate
1998-03-20
2001-08-14
Lee, Thomas C. (Department: 2782)
Electrical computers and digital processing systems: processing
Processing architecture
Long instruction word
C712S210000
Reexamination Certificate
active
06275921
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority of Japanese Patent Application No. 09-238287 filed Sep. 3, 1997, the contents being incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to the field of data processing devices including No Operation (“NOP”) instructions. More particularly, the present invention relates to data processing devices that eliminate at least NOP instructions from an instruction string to provide more efficient use of instruction storage memory. The present invention also particularly relates to data processing devices, mainly intended for a Very Long Instruction Word (“VLIW”) computer, that eliminate NOP instructions inserted substantially into a load module of the VLIW computer to compress the load module and expand the compressed load module automatically by a hardware circuit when executing instructions.
To satisfy the recent demand for faster computer systems, a computer based on a new Central Processing Unit (“CPU”) operating system called VLIW is being developed. To install a VLIW-type computer in a limited memory space, VLIW-type load modules should be made as small as possible.
A load module of a conventional VLIW-type computer contains NOP instructions. Because of the use of many unnecessary NOP instructions, the percentage of actual execution instructions in a load module is low. Therefore, if a VLIW-type computer is introduced into a computing system that has a limited memory capacity, such as dedicated processing modules, instruction storage memory is not used efficiently.
Thus, as set forth above, the low efficiency of memory use makes it difficult to use a VLIW-type computer for industrial applications.
BRIEF SUMMARY OF THE INVENTION
It is therefore an object of the present invention to solve the above-mentioned problems by providing a device that eliminates NOP instructions inserted substantially into a load module of a VLIW computer.
It is a further object of the present invention to compress a load module for a VLIW computer and expand the compressed load module automatically by a hardware circuit when executing instructions.
It is an even further object of the present invention to remove NOP instructions to thereby increase a necessary capacity in a load module of a VLIW computer.
It is a further object of the present invention to reduce module size in a VLIW computer.
Objects of the present invention are achieved by a data processing device with an instruction compression function and an instruction decompression function, including an instruction storage memory to store specific instruction code strings in a compressed form, wherein each instruction code string includes attached compression information indicating a form of compression; and an instruction code decompression circuit to restore an instruction code string read from the instruction storage memory to an original status according to the attached compression information.
Further objects of the present invention are achieved by a data processing device with an instruction compression function and an instruction decompression function, including an instruction storage memory to store at least specific instruction code strings in a compressed form with compression information indicating a form of compression; an instruction buffer to store decompressed instructions; an auxiliary buffer to temporarily store part of an instruction being decompressed; a first switch to selectively input instruction code strings of high-order slots read from the instruction storage memory into the instruction buffer; a second switch to selectively input instruction code strings of low-order slots read from the instruction storage memory into the instruction buffer and the auxiliary buffer; a third switch to transfer contents of the auxiliary buffer to the instruction buffer; and a control circuit to control the first, second, and third switch according to the compression information.
Even further objects of the present invention are achieved by a data processing device with an instruction compression function and an instruction decompression function, including an instruction storage memory to read or write instruction codes in units of instruction code strings including a predetermined number of instruction codes in a compressed form and storage position information attached to each instruction code by deleting specific instruction codes; and an instruction code decompression circuit to decompress each instruction code according to the attached storage position information.
Moreover, objects of the present invention are achieved by a data processing device with an instruction compression function and an instruction decompression function, including an instruction storage memory to read or write instruction codes in units of instruction code strings, each instruction code string including a specified number of instruction codes in a compressed form and storage position information attached to each instruction code by deleting specific instruction codes; a plurality of instructions buffers to store a plurality of instruction codes and to cyclically fetch a plurality of instructions; an instruction code distribution unit to develop a compressed instruction code string read from the instruction storage memory and send the instruction codes to respective instruction buffers of the plurality of instruction buffers; and a control circuit to control the development of a compressed instruction code string in the instruction distribution unit according to storage position information attached to each instruction code and instruction buffer information indicating an instruction buffer from which an instruction is output.
Even further objects of the present invention are achieved by a data processing device with an instruction compression function and an instruction decompression function, including an instruction storage memory to store specific instruction code strings in a compressed form with attached compression information indicating a form of compression; and an instruction code decompression circuit to restore a code string read from the instruction storage memory to an original status according to the attached compression information, wherein a program counter is not added to an instruction code deleted for compression and a program counter is added to an instruction code stored in the instruction storage memory.
Objects of the present invention are also achieved by a data processing device with an instruction compression function and an instruction decompression function, including an instruction storage memory to read or write units of instruction code strings including a predetermined number of instruction codes in a compressed form with storage position information attached to each instruction code by deleting specific instruction codes; and an instruction code decompression circuit to decompress each instruction code according to the attached storage position information, wherein a program counter is not added to an instruction code deleted for compression, and wherein a program counter is added to an instruction code stored in the instruction storage memory.
Further objects of the present invention are achieved by a data storage medium to store at least specific instruction code strings in a compressed form and compression form information respectively indicating a form of compression for the instruction code strings.
Moreover, objects of the present invention are achieved by a data storage medium to read or write instruction codes in units of instruction code strings including a specified number of instruction codes in a form compressed by deleting specific instruction codes and in a form such that storage position information is respectively attached to each instruction code.
Even further objects of the present invention are achieved by a data processing device with an instruction compression function and an instruction decompression function, including an instruction storage memory to store specific instruct
Asato Akira
Iwata Yasushi
Fujitsu Limited
Kim Harold
Lee Thomas C.
Staas & Halsey , LLP
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