Data processing device that controls an overriding of a...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...

Reexamination Certificate

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Details

C712S234000

Reexamination Certificate

active

07010670

ABSTRACT:
The invention provides a data processing device with which disadvantages due to instruction allocation and decreased memory when adding a condition specifying field for executing conditional instructions can be prevented, and in which pipeline hazards due to the non-fulfillment of conditions can be suppressed when instructions with contradicting conditions are performed successively. The data processing device reads in and executes instructions in a certain sequence, and includes a fetch portion for reading in a computational instruction, a decoding portion for decoding the computational instruction that has been read in, an execution portion for executing the decoded computational instruction, and an instruction overriding control circuit that overrides, of one or a plurality of subsequent instructions that follow the computational instruction in said sequence and are associated with the computational instruction, all but one of the subsequent instructions, in accordance with an execution result of the computational instruction.

REFERENCES:
patent: 3577189 (1971-05-01), Cocke et al.
patent: 3577190 (1971-05-01), Cocke et al.
patent: 4539635 (1985-09-01), Boddie et al.
patent: 5761467 (1998-06-01), Ando
patent: 5771377 (1998-06-01), Ando
patent: 6055625 (2000-04-01), Nakada et al.
patent: 6125443 (2000-09-01), Takahashi
patent: 62-262140 (1987-11-01), None
patent: 2-69826 (1990-03-01), None
patent: 3-269728 (1991-12-01), None
Rosenberg, Dictionary of Computers, Information Processing & Telecommunications, 2ndedition, 1987, p. 491.

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