Patent
1993-08-19
1998-10-20
Shah, Alpesh M.
395842, G06F 1300
Patent
active
058261010
ABSTRACT:
A data processing device comprising comprising a memory having a plurality of addressable memory locations, a processor circuit, an input register operative to hold input data, an output register operative to hold output data, and a direct memory access (DMA) circuit operative to receive input data from the input register for storing the input data in a first memory location and to concurrently send output data from a second memory location to said output register. Other devices, systems and methods are also disclosed.
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Beck Michael D.
Simar Laurence R.
Donaldson Richard L.
Kesterson James C.
Shah Alpesh M.
Stahl Scott B.
Texas Instruments Incorporated
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