Electrical computers and digital processing systems: processing – Processing architecture – Long instruction word
Reexamination Certificate
1998-09-01
2001-02-27
An, Meng-Ai T. (Department: 2783)
Electrical computers and digital processing systems: processing
Processing architecture
Long instruction word
C712S234000, C712S208000
Reexamination Certificate
active
06195741
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority of Japanese Patent Application No. 09-355948 filed Dec. 25, 1997, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data processing device which processes variable length code, and, more particularly, the present invention relates to a data processing device that decreases the processing time required to load variable length code from memory and the processing time required to store variable length code to memory.
2. Description of the Related Art
In the field of media processing, when storing large volume data such as image and audio data in a memory device or transmitting such data to another device, data compression is generally employed to make effective use of resources. Various methods of data compression have been proposed and executed, however, in nearly all methods, the compressed data is variable length code (abbreviated “VLC” hereinafter). Huffman code is one such representative method for compressing data resulting in variable length code.
When using custom hardware to conduct processing that compresses media data into VLC data, and restoring VLC data to media data, software has been used to improve the performance of the custom hardware processor.
A problem encountered in using the instruction set of a general processor is that it is not suitable to handle VLC due to the fragmentary length of the VLC. For example, the load/store instruction of general processors normally targets byte unit data that is byte aligned, and therefore, to configure VLC data that extends across a word boundary into a general register, two loads and several shift and logical calculations are required. In addition, because the number of required loads depends on the VLC lead offset and VLC length, a condition determination operation must be executed several times.
In this way, when using the instruction set of a conventional general processor to process VLC load/store operations, many instructions are necessary, and therefore, it is likely that this will create a significant performance overhead.
The present invention has the purpose of addressing the problems encountered in manipulating VLC data, and resolving these problems by offering a variable length code processing mechanism suitable for handling VLC data.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a data processing device which efficiently processes variable length code (“VLC”).
Objects and advantages of the present invention are achieved by a data processing device having a variable length code processing mechanism which includes the following elements. An address register is used to store access addresses in a memory. A first buffer register is used to store data loaded from the memory and where the first buffer register has a bit width at least equal to a load data width from the memory. A second buffer register is connected to the first buffer register. The contents of the first buffer register are shifted and stored into the second buffer register. An offset register stores the length of an empty region produced in a linked region which is configured by linking the first buffer register and the second buffer register when the data is packed and stored into an unlinked end of the second buffer register. A first processing unit is used to shift the data which exists in the linked region and which is packed and stored in the unlinked end of the second buffer register, to the unlinked end of the second buffer register by a specified amount. Simultaneously the first processing unit increments the offset register value by the shift amount. A second processing unit loads the data held in memory addressed by the value of the address register, in the first buffer register, and simultaneously increments the value of the address register by a specified amount when the value of the offset register is equal to or greater than the value of a bit width of the first buffer register. However, the second processing unit takes no action when the value of the offset register is less than the bit width of the first buffer register. When the value of the offset register is equal to or greater than the value of the bit width of the first buffer register, a third processing unit shifts the contents of the first buffer register, which the second processing unit has loaded from memory, to the second buffer register by a number of bits equal to the contents of the offset register minus the first buffer register bit width. The third processing unit then substitutes a bit portion of the linked end of the second buffer register, which is equal to the contents of the offset register minus the first buffer register bit width, with the bits shifted out from the first buffer register, and simultaneously decrements the value of the offset register by the number of the buffer register bits. However, the third processing unit takes no action when the value of the offset register is less than the bit width of the first buffer register.
Further objects of the present invention are achieved by a data processing device having a variable length code processing mechanism which includes the following elements. An address register stores access addresses in memory. A first buffer register, having a bit width at least equal to a load data width from the memory, stores data loaded from the memory. A second buffer register is connected to the first buffer register. The contents of the first buffer register are shifted and stored into the second buffer register. An offset register is used to store the length of an empty region produced in a linked region which is configured by linking the first buffer register and the second buffer register when the data is packed and stored into an unlinked end of the second buffer register. A first shift instruction that designates a shift amount as an operand, shifts the data existing in the linked region to the unlinked end of the second buffer register by the shift amount, and simultaneously increments the offset register value by shift amount. A conditional load instruction loads the data held in memory addressed by the value of the address register, in the first buffer register, and simultaneously increments the value of the address register by a specified amount when the value of the offset register is equal to or greater than the value of a bit width of the first buffer register. However, the conditional load instruction takes no action when the value of the offset register is less than the bit width of the first buffer register. When the value of the offset register is equal to or greater than the value of a bit width of the first buffer register, a second shift instruction is used to shift the contents of the first buffer register, which the conditional load instruction has loaded from memory, to the second buffer register by a number of bits equal to the contents of the offset register minus the first buffer register bit width. The second shift instruction then substitutes a bit portion of a linked end of the second buffer register, which is equal to the contents of the offset register minus the first buffer register bit width, with the bits shifted out from the first buffer register, and simultaneously increments the value of the offset register by the number of the buffer register bits. However, the second shift instruction takes no action when the value of the offset register is less than the bit width of the first buffer register.
In accordance with embodiments of the present invention, the data processing device further includes the following elements. A second offset register is used to set a difference between the shift amount specified as the operand of the first shift instruction and the bit width of the first buffer register. A flag register is set when the first shift instruction designates the shift amount that exceeds the bit width of the first buffer register. When the value of the second offset reg
An Meng-Ai T.
Chang Jung W.
Fujitsu Limited
Staas & Halsey , LLP
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