Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2001-10-11
2003-12-23
Ngo, Chuong Dinh (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S524000
Reexamination Certificate
active
06668266
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor large-scale integrated circuit having a central processing unit (CPU) and a digital signal processing unit, and more specifically to a technology suitably applied to data processing devices, such as microcomputers and digital signal processors, that require high calculation speeds.
An example of a microcomputer, which has mounted on a single chip the central processing unit (CPU) for controlling an entire system and the digital signal processing unit (digital signal processor (DSP)) having a product sum function required for efficient processing of digital signals, is found in “SH Series Incorporating DSP Function” by Kawasaki, et al., Nikkei Electronics, Nov. 23, 1992 issue, no. 568, pp. 99-112.
According to this literature, the digital signal processing unit having the product sum function is able to execute representative calculations of digital signal processing, such as digital filtering, efficiently in a small number of steps.
SUMMARY OF THE INVENTION
The conventional digital signal processing unit described in the above literature, though it has a product sum calculator, handles data to be calculated as integer data as in the central processing unit. Data handled in the world of digital signal processing are generally fixed-point or floating-point data. The floating-point data has a data format consisting of mantissa data and exponent data and is totally different from integer data, whereas the fixed-point data looks very similar to integer data except that the binary point position is different. Actually, the adding and subtracting calculation on the fixed-point data performs basically the same processing as the integer data.
Multiplication, however, uses lower-order words of specified registers as source data in the case of integer data but, in the case of the fixed-point data, uses higher-order words of specified registers, as shown in FIG.
1
(
a
). This is because a part of data closer to the binary point is more important and, as shown in FIG.
1
(
b
), the integer data is regarded to have the binary point to the right of the least significant bit whereas the fixed-point data normally has the point immediately to the right of the most significant bit. Hence, for an integer multiplier to carry out fixed-point multiplication, the source data needs to be shifted from the higher-order side to the lower-order side beforehand. Further, as shown in FIG.
1
(
c
), digit aligning is performed based on the binary point position, producing a one-bit position difference between the integer data and the fixed-point data. This requires the actual program to perform shift processing to correct the bit positional difference.
There is another problem. When data read out from memory or calculation results are stored in memory or output to external devices, the digital signal processing often allows the bit length of such data to have a lower bit precision than during calculation. Hence, the actual digital signal processing unit generally performs data transfer to and from memory or external circuits in single precision words (for example, 16-bit words) and calculations in double precision words (for example, 32-bit words). When transferring data whose bit length is shorter than these calculation precisions, the operations performed on integer data and on fixed-point data greatly differ.
When transferring word data and byte data (8 bits long) whose bit length is short, the calculator dedicated to handling integer data inputs and outputs the lower-order side of a register that stores data. However, the calculator dedicated to handling fixed-point data inputs and outputs the higher-order side of the data. This difference is caused by the differing positions of the binary point. That is, when the bit length of the data to be transferred is shorter than the bit length of the operand to be stored, a part of the data closer to the binary point is more important from the standpoint of data precision and range. This binary point is assumed to be located to the right of the least significant bit in integer data whereas the binary point in fixed-point data is usually located immediately to the right of the most significant bit. This causes the above-mentioned difference in the data handling. As a result, a problem arises that the shift processing must be done each time a calculator designed to handle integer data transfers data whose bit length is shorter than the calculation precision.
If the bit length of data during transfer is set equal to the bit length of data during calculation, no such problem will occur. But transfer of redundant bits raises a problem of requiring an additional bus width and an additional memory capacity for storing data.
An object of the present invention is to provide a data processing device, such as a microcomputer and a digital signal processor, incorporating a central processing unit and a digital signal processing unit that processes fixed-point data.
Another object of the present invention is to prevent the number of processing steps from being increased by the difference in the type of data handled by the calculator and thereby enhance the efficiency of the digital signal processing in the microcomputer and the digital signal processor, which have mounted on a single chip a central processing unit for controlling the whole system and a digital signal processing unit having a product sum function for efficiently processing digital signals.
A further object of the present invention is to eliminate additional shift operations required by the correction of bit positions of multiplication results and by the data transfer, thereby increasing the speed of the digital signal processing.
These and other objects and novel features of the present invention will become apparent from the following description in this specification and the accompanying drawings.
Representative aspects of this invention may be briefly summarized as follows.
(a) The data processing device (
1
) has mounted on a single semiconductor substrate a CPU (
100
) and a digital signal processing unit (
104
) whose operation is controlled by the CPU (
100
) decoding instructions. The digital signal processing unit (
104
) has an addition/subtraction circuit (
105
) for fixed-point data and a multiplier (
106
) for fixed-point data.
(b) The data processing device (
1
) has a first processing unit (
100
) and a second processing unit (
104
), the first processing unit including a first register (
103
) and first calculators (
101
,
102
) for performing operations on data contained in the first register (
103
), the second processing unit including a second register (
108
) and second calculators (
105
,
106
) for performing operations on data contained in the second register (
108
). The first processing unit (
100
) processes integer data and the second processing unit (
104
) processes fixed-point data.
(c) The digital signal processing unit (
104
) has a register (
108
) and calculators (
105
,
106
) for processing data in the register (
108
). When performing a first instruction for transferring data whose bit length is shorter than the bit length of the register (
108
) from outside the data processing device to the register (
108
), the data processing device (
104
) takes and justifies data to the higher-order side of the register (
108
) and setting zeros at the redundant lower-order side of the register (
108
). When performing a second instruction for transferring data whose bit length is shorter than the bit length of the register (
108
) from the register (
108
) to the outside of the data processing unit (
104
), the data processing unit (
104
) outputs a required bit length of data beginning with the higher-order side of the register (
108
).
(d) The data processing device (
1
) has a central processing unit (
100
) including a calculation circuit (
101
) that performs arithmetic operation or logic operation; first, second and third address buses (
109
,
110
,
111
) to which addresses are selectively transf
Akao Yasushi
Baba Shiro
Baji Toru
Hatano Yuji
Kiuchi Atsushi
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
Ngo Chuong Dinh
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