Data processing device for variable word length instruction syst

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364DIG1, 364DIG2, 3642318, 364259, 3642598, 3642599, 36426281, 3642328, 3649278, 3649256, 364947, 3649515, G06F 930

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054524270

ABSTRACT:
A first instruction bit string following a memory position indicated as a start point by a read pointer is previously read out from a plurality of memory cells to a plurality of bit lines, a second instruction bit string already transferred to an instruction decoder is temporarily stored in a latch circuit by an instruction length notification signal output from said instruction decoder, and a select circuit selects a next instruction bit string sequentially continuing from a next instruction, between the first and second instruction bit strings without requiring other bit lines or word lines. Therefore, a high speed instruction processing in the pipeline processing can be obtained with a minimum number of transistors and associated wiring required for memory cells in an instruction buffer memory. Large scale integration, small size, and a low cost can therefore be realized.

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