Boots – shoes – and leggings
Patent
1986-09-02
1989-12-26
Eng, David Y.
Boots, shoes, and leggings
364736, 3649291, 36493102, 36493151, G06F 1202, G06F 15347
Patent
active
048902551
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
This invention relates to digital computers and more particularly to computer memory circuitry.
BACKGROUND ART
In computer techniques, memory structures are presently, in the last analysis, in the form of sets of individually-addressable locations each of which is disjoint from the others. In many situations, it may happen that the user is unaware of this partitioning, but the constraint remains at the finest level internally. Various techniques have been implemented for mitigating this constraint, using hardware, software, or even by combining both. Escaping from partitioning consists in being able to "slide" through memory space while accessing overlapping locations without being obliged to operate on segmented space by jumping from one segment to another. In order to mitigate these drawbacks, there exists the resource at the highest level of evolved languages, while at machine level it is possible to use a single processor instruction to access data straddling two memory segments, however in this case it is, in fact, the microprogram which performs the necessary memory accesses. Finally, use may be made of combined hardware/software techniques which are based on memories as presently structured and which associate auxiliary address analyzing and calculating devices therewith, which devices must be passed through in order to access the memory per se. In each of these cases it is common practice to use inexact language referring to "simultaneous" or "instantaneous" access. However, the situation of maximum command parallelism activating a plurality of elementary memory cells (as when accessing a physical memory segment) does not then occur. The concepts explained in patent No. 84 12946 (Aug. 16th, 1984) are extended herein.
SUMMARY OF INVENTION
(1) The problem of generating commands.
This is a problem of defining a new memory structure which is accessible via a window of fixed dimensions at any memory location and under conditions of maximum speed. Rather than using existing memory packages, the intention here is to design novel packages. In order to do this, it is necessary to define special methods and devices for generating simultaneous command trains, and applications other than those described herein may be imagined for such methods and devices. These methods and devices are therefore described herein in a self-contained manner. Further, although the technical context of the invention is hardware, this term is used in its widest sense without any a priori limitation to any specific technology. Essentially, in order to implement the methods and devices described, it is necessary to have conventional components for performing binary logic functions, and these may be made in all sorts of technologies: use is thus made of one-way and two-way binary data transmission channels, conventional Boolean devices such as AND gates, OR gates, etc., and functional means of the three-state buffer type which act as on/off switches on the data transmission channels.
BRIEF DESCRIPTION OF DRAWINGS
FIGS. 1 and 2 are intuitive images for facilitating understanding of the methods Pro1 and Pro'1; they are described above in the description.
FIG. 3 shows permutating means Perm(h) for the case when h=4, and providing 4 circular permutations: (q=0)); (q=1)); (q=2)); (q=3));
This device is described above.
FIG. 4 shows permutating means Perm(h,h') comprising h' devices of the type Perm(h) and h of the type Perm(h'), for the case where h=h'=4; it is used in the context of problems P.sub.2 (M) and P'.sub.2 (M), and it is described above.
FIG. 5 is associated with problem p.sub.1 ; it shows a device referenced DChN(a)1, of the type DChN(a) (see above).
FIG. 6 is also associated with the problem p.sub.1 and shows a device DChN(a)2 of the type DChN(a).
FIG. 7 is associated with the problem p'.sub.1, and represents a device reference DRhN(a)1 of the type DRhN(a) (see above).
FIG. 8 is also associated with problem p'.sub.1, and shows a device DRhN(a)2 of the type DRhN(a).
FIG. 9 is associated with p.sub.1 and
REFERENCES:
patent: 3651495 (1972-03-01), Sauvan
patent: 3996559 (1976-12-01), Morrin et al.
patent: 4570236 (1986-02-01), Rebel et al.
patent: 4709327 (1987-11-01), Hillis et al.
"Design and Performance of Generalized Interconnection Networks", IEEE Transactions and Computers, vol. C32, No. 12, Dec. 12, 1983, New York, U.S.A., L. N. Bhuyan et al.
Isoardi Patrick
Lehmann Jean-Philippe
Chan Emily Y.
Eng David Y.
LandOfFree
Data processing device for simultaneously activating and applyin does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Data processing device for simultaneously activating and applyin, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data processing device for simultaneously activating and applyin will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1580738