Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate plural instruction...
Reexamination Certificate
1998-10-01
2001-10-02
An, Meng-Al T. (Department: 2154)
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate plural instruction...
C712S205000, C712S208000, C709S241000
Reexamination Certificate
active
06298434
ABSTRACT:
Unpublished European patent application No. 97203033.2 improves the speed with which programs expressed in the virtual machine instruction set are processed. This is achieved by adding a preprocessor between the memory and the processor core. The preprocessor stores for each particular virtual machine instruction one or more native instructions that express the function of that particular machine instruction. The preprocessor reads a virtual machine instruction from memory, selects the native instruction or instructions defined for that virtual machine instruction and supplies this instruction or these instructions to the processor core for execution. The processor core executes the native instructions that perform the function defined by the virtual machine instruction consecutively: between the clock cycles for those native instructions no processor core clock cycles are used in which the processor core executes additional instructions to select the appropriate native instructions.
In addition, the processing device of European patent application No. 97203033.2 is also capable of executing native instructions from the memory without translation by the preprocessor. This is done on the basis of the instruction address issued by the processor core: the preprocessor will supply translated native instructions only when the instruction address issued by the processor core is in a predefined address range; otherwise the memory content of the addressed location is supplied to the processor core.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the field of data processing devices using virtual machine instructions.
2. Related Art
A processor core normally is capable of executing instructions from a native instruction set only. For various reasons it is desirable that such a processor core is able to process programs expressed in an other instruction set than this native instruction set. In this way a standard processor core may be used without hardware modifications for example to emulate processing by a different processor core, e.g. a core for executing Java instructions. Such another instruction set in which a program is expressed, but which is not the native instruction set whose instructions the processor core is capable of executing, will be called a virtual machine instruction set.
Conventionally, processing of instructions from the virtual machine instruction set is realized by means of an interpreter program which is executed by the processor core. This is exemplified by U.S. Pat. No. 4,443,865. For each virtual machine instruction the interpreter program contains a corresponding execution program expressed in native instructions. The interpreter causes the processor core to read a virtual machine instruction from memory, to select the address of the execution program for the virtual machine instruction and to transfer control of the processor core to that execution program. Such processing by means of an interpreter is intrinsically slower than direct execution, because the processor core needs to spend processing cycles on the selection of addresses of execution programs and transfer of control in addition to the processing cycles needed to perform the functional tasks of the execution program.
It has been found that translation of virtual machine instructions by a preprocessor, although generally satisfactory, reduces the flexibility of the definition of the meaning of virtual machine instructions and that a few of the virtual machine instructions require excessive memory in the preprocessor.
SUMMARY OF THE INVENTION
It is an object of the invention to make the data processing device with a preprocessor between the memory and the processor core more flexible.
The data processing device according to the invention is characterized by the preprocessor being arranged for
reading a further virtual machine instruction of a special type from the memory,
retrieving a target address which has been predefined for a further special type and
causing the processor core to execute a subroutine of the native instructions located in the memory at a location indicated by the target address in response to
the further virtual machine instruction.
Thus in response to a selected virtual machine instruction (the further virtual machine instruction) the preprocessor causes the processor core to execute a native subroutine from memory instead of normally supplying locally stored native instructions to the processor core. In this way the preprocessor provides for virtual machine program execution by a mix of consecutive execution of translated instructions and native subroutine execution. Processing virtual instructions by subroutine calls is comparable to the way conventional interpreters process virtual instructions, except that the preprocessor instead of the processor core generates the native subroutine call instruction from the further virtual instruction. In this way a minimum of processing cycles of the processor core is lost.
Upon return from the native subroutine the preprocessor resumes supplying translated native instructions to the processor core. To detect the return the preprocessor may for example monitor the instruction addresses issued by the processor core.
In an embodiment of the processing device according to the invention the preprocessor makes it possible to call a subroutine compiled from a high level language. Virtual machine instructions expect to find their arguments in storage locations as defined by a first argument storage convention. High level language compilers often assume the existence of a “context” when calling a subroutine. This context usually involves arguments for the subroutine that are stored at specific, predefined storage locations, such as a number of predefined registers and/or memory locations pointed at by a stack pointer register. The definition of these storage locations is fixed by a second argument storage convention, which defines the storage locations in a uniform way for all subroutines in the high level language.
Generally this second storage convention will differ from the first argument storage convention used by the high level language, for example because no specific registers are defined as locations for arguments.
To make use of subroutines compiled from such high level languages the invention provides for a data processing device wherein
the preprocessor monitors whether instruction addresses issued by the processor core are inside a predetermined range, an instruction address range of the subroutine lying outside the predetermined range,
the preprocessor detects completion of the subroutine when the processor core from issues an instruction address inside the predetermined range after transfer of control to the subroutine.
When the preprocessor issues native instructions to the processor core that cause it to transfer control to such a subroutine that the preprocessor fist causes the processor core to transfer the arguments from the storage locations defined by the first storage convention (used for the arguments of virtual machine instructions) to the storage locations defined by the second argument storage convention before actually transferring control to the subroutine.
More generally the invention also relates to a data processing device including a processor. The processor has an instruction set containing first instructions. Each first instruction causes the processor to execute a respective operation before executing a directly succeeding instruction from the instruction set. The respective operations each use one or more arguments. The arguments are stored at storage locations predefined by a first argument storing convention. The instruction set also contains a special instruction which causes the processor to jump to a subroutine. The subroutine uses one or more arguments stored at storage locations predefined by a second argument storing convention. The processor transfers the one or more arguments to the storage locations predefined by the second argument storing convention from storage
An Meng-Al T.
Lin Wen-Tai
U.S. Philips Corporation
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