Data processing device for maintaining coherency of data stored

Details Data processing device for maintaining coherency of data stored Data processing device for maintaining coherency of data stored

1993-08-23

1995-10-03

MacDonald, Allen R.

Boots, shoes, and leggings

364DIG1, 36424345, 3642461, 3642543, 395473, G06F 1206, G06F 1300

Patent

active

054559251

ABSTRACT:
A fetching operation break unit breaks a fetching operation of a block data from a main memory, when a system bus is released during the fetching of the block data and also when data written due to a write access by an external device into the main memory coincides with the fetching of one block data. Further, a notification means notifies the state of the fetching operation to an external cache memory. Therefore, the external cache memory can confirm whether a block-in operation of the microprocessor is broken or not, and the contents of the external cache can correctly coincide with the contents of the internal cache and the main memory by carrying out a steal operation, so that the operational reliability of a computer system can be increased.

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Electronic Engineering, vol. 59, No. 730, Oct. 1987, pp. 57-63; D. Schanin: "Cache Coherency In Microprocessor Based Systems", Figs. 7, 8; p. 60, left-hand col., line 15--p. 63, right-hand col., line 24.
Computer Society International Conference (Compcon) Conference No. 33, spring 1988, pp. 218-222, IEEE, New York, US; L. Quinones: "The NS32605 Cache Controller", Fig. 1; p. 220, lines 7-49.

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