Data processing device designing method, data processing...

Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation

Reexamination Certificate

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Reexamination Certificate

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07447617

ABSTRACT:
A method includes steps of calculating, for each predetermined operation included in a program, an execution time required when the operation is executed by a predetermined processor, or calculating, for each predetermined operation included in the program, a circuit size required when the operation is realized in a form of hardware according to a predetermined technology; and calculating, for the entirety of the predetermined program or operations corresponding to a part the entirety of the predetermined program, a total execution time required when the entirety of the predetermined program is executed by the predetermined processor, as a result of applying in sequence the required execution time, or calculating, for the entirety of the predetermined program or operations corresponding to a part the entirety of the predetermined program, a total circuit size required when the entirety of the predetermined program or programs corresponding to a part of the entirety of the predetermined program, as a result of applying in sequence the required circuit size.

REFERENCES:
patent: 5832202 (1998-11-01), Slavenburg et al.
patent: 7228262 (2007-06-01), Anzou et al.
patent: 2001/0005880 (2001-06-01), Ando
patent: 4-199439 (1992-07-01), None
patent: 2000-187675 (2000-07-01), None
patent: 2000-305967 (2000-11-01), None
patent: 2002-269163 (2002-09-01), None
Eunmi et al., C. An Important Factor for Optimistic Protocol on Distributed Systems: Granularity, IEEE Winter Simulation Conference, Dec. 1995, pp. 642-649.
Chung et al., M. An Overhead Reducing Technique for Time Warp, Sixth IEEE Workshop on Distributed Simulation and Real-Time Applications, Oct. 2002, pp. 95-102.
Obermeier, F. A Model Generation and Compilation System for Improving Electrical Performance, IEEE Symposium on Circuits and Systems, May 1990, pp. 852-855.
Jayabharathi et al., R. A Novel Solution for Chip-Level Functional Timing Verification, 15th IEEE VLSI Test Symposium, Apr.-May 1997, pp. 137-142.

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