Image analysis – Image transformation or preprocessing – Image storage or retrieval
Reexamination Certificate
2000-05-08
2003-04-29
Mehta, Bhavesh (Department: 2625)
Image analysis
Image transformation or preprocessing
Image storage or retrieval
C382S296000, C382S289000, C382S239000, C382S236000, C348S397100, C348S395100
Reexamination Certificate
active
06556725
ABSTRACT:
TECHNICAL FIELD
This invention relates to a data processing device and a data order converting method, and particularly to a data processing device and a data order converting method which enable output, in a predetermined order, of pixels inputted in a line scan order.
BACKGROUND ART
In the case where, for example, digital image data is to be transmitted (communicated) via a satellite link, the Internet or any other communication network, and in the case where digital image data is to be recorded to a recording medium such as a digital VTR (video tape recorder) or DVD (digital versatile disc), shuffling or scrambling is often performed on the image data for the purpose of noise prevention, security on the network and protection of copyright and broadcasting right. Shuffling is carried out by rearranging pixels arranged in the line scan order constituting an image.
In motion detection in conformity to the MPEG (Moving Picture Experts Group), which is a standard for image coding/decoding, block matching is carried out between a block consisting of 8×8 pixels of a current frame as a processing target and a block of pixels within a search range of a temporally preceding (past) frame or a temporally succeeding (future) frame as a reference frame for the current frame. In such case, the search range must be detected from the reference frame, which is one frame. In the case where the search range is detected from one frame, when the image is supplied in the line scan order and stored into a memory, a number of pixels equal to the number of lateral pixels of the search range must be taken out by reading a number of lines equal to the number of longitudinal pixels of the search range from the memory and then cutting the read lines in the vertical direction. Therefore, the search range is detected by converting a plurality of lines of the reference frame constituted by pixels arrayed in the horizontal order to an image constituted by pixels arrayed in the vertical order, that is by rearranging the pixels arranged in the line scan order constituting the plurality of lines of the reference frame.
Moreover, rotation of an image by 90 degrees can be carried out by converting an image constituted by pixels arrayed in the horizonal order to an image constituted by pixels arrayed in the vertical order. Therefore, it can be carried out by rearranging the pixels arranged in the line scan order constituting the image.
Such technique of rearranging pixels constituting an image is used for various types of image processing.
FIG. 1
shows the structure of an example of a conventional image rearrangement device for converting an image constituted by pixels arrayed in the horizontal order to an image constituted by pixels arrayed in the vertical order.
In
FIG. 1
, digital image data to be a processing target is supplied to a parallel/serial conversion circuit
301
as parallel data of every four pixels as a unit in the line scan order. The parallel/serial conversion circuit
301
converts the parallel data supplied thereto of every four pixels as a unit to serial data and sequentially supplies the serial data to line memories
302
to
305
each having a storage capacity for one line.
The line memory
302
stores pixels from the parallel/serial conversion circuit
301
. The pixels stored in the line memory
302
are shifted rightward every time pixels are newly supplied from the parallel/serial conversion circuit
301
. Specifically, in the case where one pixel is noted, when pixels of one line are supplied after the noted pixel is supplied to the line memory
302
, the noted pixel is outputted from the line memory
302
and supplied to the subsequent line memory
303
.
Also, in the line memory
303
, similar to the line memory
302
, the pixels supplied from the line memory
302
are delayed by one line and supplied to the subsequent line memory
304
. Similarly, the pixel data is delayed by one line in the line memories
304
and
305
, respectively.
Therefore, in the case where certain four consecutive lines are noted, the pixels of the same column of the four lines are outputted in parallel from the line memories
302
to
305
. Thus, in the rearrangement device of
FIG. 1
, four lines of an image constituted by pixels arrayed in the horizonal (row or lateral) direction is converted to an image constituted by pixels arrayed in the vertical (column or longitudinal) direction.
In the conventional technique, as described above, in the case where pixels constituting an image are to be rearranged, a number of line memories corresponding to the number of lines on which pixels are to be rearranged are required. Since each of the line memories need to have a storage capacity for one line constituting the processing target image, line memories having a large storage capacity are required in the case where the processing target image is a highly fine image used for HDTV (high definition television) or the like.
Moreover, the line memory is generally made up of an SRAM (static random access memory). Since an SRAM has a chip size approximately 10 to 20 times that of a DRAM (dynamic RAM) of the same capacity, the use of SRAMs for line memories causes an increase in the chip size in realizing LSI (large scale integration) of the device.
Meanwhile, as a technique for rearranging pixels constituting an image, other than the technique of rearranging pixels using line memories as buffers as shown in
FIG. 1
, there is a technique of preparing a frame memory for storing an image and then scrambling or shuffling either a write address used for writing the image to the frame memory or a read address used for reading the image stored in the frame memory. As a method for scrambling the write address or read address, a memory for address conversion having a scrambled address stored therein is prepared and the write address or read address is supplied to the memory for address conversion, thereby using the address outputted from the memory for address conversion as the scrambled address.
FIG. 2
shows the structure of an example of a conventional shuffling memory device for shuffling image data by scrambling a write address or read address.
The shuffling memory device is supplied with 8-bit image data, a write pulse, a read pulse and a write enable signal WE, which are shuffling targets. The image data is supplied to an I/O (input/output) selector
201
. The write pulse is supplied to a write address counter
202
. The read pulse is supplied to a read address counter
203
. The write enable signal WE is supplied to the I/O selector
201
, a selector
205
and a RAM (random access memory)
206
.
In this shuffling memory device, the image data supplied to the I/O selector
201
is written to the RAM
206
. After that, in reading the image data from the RAM
206
, the read address is controlled. Thus, shuffling of the image is performed.
Specifically, at the time of writing the image data, the write enable signal WE is set at H-level indicating writing, of H (high)-level and L (low)-level, and is supplied to the I/O selector
201
, selector
205
and RAM
206
. On receiving the write enable signal WE of H-level, the I/O selector
201
selects image data to be a shuffling target and supplies the selected image data to an input/output terminal (I/O) of the RAM
206
.
When the write enable signal WE is set at H-level, the write pulse starts to be supplied to the write address counter
202
. In accordance with the write pulse, the write address counter
202
makes increment on the 8-bit count value by one. The 8-bit count value is outputted as a write address to the selector
205
.
When receiving the write enable signal WE of H-level, the selector
205
selects the output from the write address counter
202
and supplies it to an address terminal (Address) of the RAM
206
. Therefore, in this case, the write address outputted from the write address counter
202
is supplied to the RAM
206
via the selector
205
.
In accordance with the write address supplied via the selector
205
, the RAM
206
stores the image data s
Ichikawa Tsutomu
Kondo Tetsujiro
Okumura Akihiro
Sato Hiroshi
Bell Boyd & Lloyd LLC
Kassa Yosef
Sony Corporation
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