Data processing device

Details Data processing device Data processing device

2007-08-07

2007-08-07

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Powering

Data preservation

C365S185230, C365S185270, C365S227000

Reexamination Certificate

active

11138344

ABSTRACT:
A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors having drain electrodes and source electrodes respectively coupled to bit lines and source lines and gate electrodes coupled to word lines and storing information based on a difference between threshold voltages to a word line select level in read operation, and the nonvolatile memory has a low power consumption mode. In the low power consumption mode, a second voltage lower than a circuit ground voltage and higher than a first negative voltage necessary for read operation is supplied to the well regions and word lines. When boost forming a rewriting negative voltage therein, a circuit node at a negative voltage is not the circuit ground voltage in the low power consumption mode.

REFERENCES:
patent: 5905685 (1999-05-01), Nakamura et al.
patent: 5920226 (1999-07-01), Mimura
patent: 2001/0013769 (2001-08-01), Saito
patent: 60-95794 (1985-05-01), None
patent: 09213913 (1997-08-01), None

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