Data processing device

Details Data processing device Data processing device

2007-07-24

2007-07-24

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185150, C365S185050

Reexamination Certificate

active

11140741

ABSTRACT:
A data processing device which selects either emission of electrons from a nonvolatile memory cell or injection of electrons into it for each bit. A memory array includes a plurality of nonvolatile memory cells each having a pair of a first MOS transistor and a second MOS transistor where the first transistor has a charge retention layer and a memory gate and is used for data storage and the second transistor has a control gate and selectively connects the first transistor to a bit line. When negative voltage is applied to a memory gate, electrons held by a charge retention layer are emitted through hot carriers generated in a nonvolatile memory cell channel region for erasing; and when positive voltage is applied to the memory gate, electrons are injected into the charge retention layer through hot carriers generated in the nonvolatile memory cell channel region for writing and controls the generation and suppression of hot carriers by means of bit line voltage on each bit line.

REFERENCES:
patent: 5912843 (1999-06-01), Jeng
patent: 2004/0257871 (2004-12-01), Swift et al.
patent: 2003-46002 (2003-02-01), None
T. Tanaka et al. , “A 512kB MONOS type Flash Memory Module Embedded in a Microcontroller,” 2003 Symposium on VLSI Circuits Dig., pp. 211-212.

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