Data processing condition code flags

Details Data processing condition code flags Data processing condition code flags

1996-10-08

1998-05-05

Mai, Tan V.

Boots, shoes, and leggings

364749, G06F 700, G06F 738

Patent

active

057485151

ABSTRACT:
A data processing system incorporating an arithmetic logic unit 20, 22, 24 having an N-bit data pathway and supporting parallel operation program instruction words in which to independent arithmetic operations are carried out in parallel by the arithmetic logic unit upon (N/2)-bit input operand words. Two sets of condition code flags N, Z, C V, SN, SZ, SC, SV responsive to the separate arithmetic logic operations are provided.

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patent: 4707800 (1987-11-01), Montrone et al.
patent: 4768160 (1988-08-01), Yokoyama
patent: 5189636 (1993-02-01), Patti et al.
patent: 5327369 (1994-07-01), Ashkenazi
patent: 5390135 (1995-02-01), Lee et al.
patent: 5479365 (1995-12-01), Ogura
patent: 5640578 (1997-06-01), Balmer et al.

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