Data processing circuits and interfaces

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...

Reexamination Certificate

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C712S223000, C712S221000, C712S036000, C711S212000, C710S307000, C713S323000, C708S205000, C708S209000, C708S503000, C708S504000

Reexamination Certificate

active

06901503

ABSTRACT:
An integrated circuit contains a microprocessor core, program memory and separate data storage, together with analog and digital signal processing circuitry. The ALU is 16 bits wide, but a 32-bit shift unit is provided, using a pair of 16-bit registers. The processor has a fixed length instruction format, with an instruction set including multiply and divide operations which use the shift unit over several cycles. No interrupts are provided. external pins of the integrated circuit allow for single stepping and other debug operations, and a serial interface (SIF) which allows external communication of test dat or working data as necessary. The serial interface has four wires (SERIN, SEROUT, SERCLK, SERLOADB), allowing handshaking with a master apparatus, and allowing direct access to the memory space of the processor core, without specific program control. Within each processor cycle, the processor circuitry is divided into plural stages, and latches are interposed between the stages to minimize power consumption.

REFERENCES:
patent: 3611309 (1971-10-01), Zingg
patent: 3975712 (1976-08-01), Hepworth et al.
patent: 4342082 (1982-07-01), Brown et al.
patent: 4486750 (1984-12-01), Aoki
patent: 4561066 (1985-12-01), Emmons et al.
patent: 4785393 (1988-11-01), Chu et al.
patent: 5274770 (1993-12-01), Khim Yeoh et al.
patent: 5293558 (1994-03-01), Narita et al.
patent: 5668970 (1997-09-01), Cowart et al.
patent: 5678025 (1997-10-01), Ghori et al.
patent: 0020185 (1980-12-01), None
patent: 0055370 (1982-07-01), None
patent: 0108664 (1984-05-01), None
patent: 0124402 (1984-11-01), None
patent: 0171190 (1986-02-01), None
patent: 0234187 (1987-09-01), None
patent: 0242003 (1987-10-01), None
patent: 0254648 (1988-01-01), None
patent: 0394499 (1990-10-01), None
patent: 1435406 (1976-05-01), None
patent: 1593136 (1981-07-01), None
patent: 2142507 (1985-01-01), None
patent: 2159987 (1985-12-01), None
“High-Speed Real-Time Event Processor”,IBM Technical Disclosure Bulletin, vol. 30, No. 2, IBM Corporation, New York, 632-634, (Jul. 1987).
“Transfer of Subsystem Control Blocks and Termination Status Blocks Between System and Subsystem by Registers”,IBM Technical Disclosure Bulletin, vol. 37, No. 9, IBM Corporation, New York, 147-148, (Sep. 1994).
Clarke, P., “Mini MPU Aims at ASICs”,Electronic Engineering Times, 24, (Mar. 1991).

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