Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
Reexamination Certificate
2000-11-22
2001-10-23
Donaghue, Larry D. (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate variable length...
C712S226000
Reexamination Certificate
active
06308258
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a data processing circuit and the semiconductor integrated circuit device, a microcomputer comprising such a data processing circuit, and electronic equipment comprising such a microcomputer.
2. Description of Related Art
At present, a Reduced Instruction Set Computer (RISC)-architecture microcomputer that is capable of handling 32-bit data uses instruction codes of a fixed 32-bit width. The use of fixed-length instruction codes makes it possible to shorten the time required for decoding the instructions, in comparison with an architecture that uses variable-length instruction codes, and it also enables a reduction in the size of the circuitry of the microcomputers.
However, a 32-bit width is not particularly necessary for many instruction codes, even in a 32-bit microcomputer. Therefore, if all the coding of instructions has to be written to fit a 32-bit width, many of the instructions will generate unnecessarily long portions in the coding, reducing the efficiency of memory usage.
In such a case, it is possible to compress unnecessarily long instruction codes by logical means and execute the instructions while decoding them on the fly within the microcomputer. However, this method raises a problem in that it requires complicated control circuitry.
The present inventors have therefore investigated the use of a microcomputer that handles fixed-length instruction codes of a bit width that is less than that of data that the microcomputer handles, in order to improve the efficiency of memory usage without using complicated control circuitry.
However, if, for example, 32-bit fixed-length instruction codes were simply converted into 16-bit fixed-length coding, the problem described below will arise.
Since each instruction code contains an operation code and operands other than immediate data, the number of bits of immediate data that can be used is much less than 16bits, even when 16-bit instruction codes are used. In other words, Ha the problem arises that less than 16bits of immediate data can be specified by an instruction code, regardless of whether the architecture can handle 32-bit data.
It is also difficult to ensure fields for the operands of a three-operand instruction with 16-bit instruction codes. This causes problems in that it is not clear how to handle operations that are difficult to express as such short instruction codes.
In order to solve the above described problem, it is necessary to have a function that can expand the immediate data comprises within short instruction codes, as necessary. It is also necessary to have a function that can expand operational details, in order to execute operations that cannot be written into short instruction codes.
SUMMARY OF THE INVENTION
An objective of this invention is to provide a data processing circuit, semiconductor integrated circuit device, microcomputer, and electronic equipment which are capable of expanding immediate data that is comprised within instruction codes, as necessary, without needing complicated control circuitry.
Another objective of this invention is to provide a data processing circuit, semiconductor integrated circuit device, microcomputer, and electronic equipment which are capable of expanding. operational details, without needing complicated control circuitry.
In order to achieve the above objectives, a first aspect of this invention relates to a data processing circuit to which are input a certain target instruction and a prefix instruction for expanding the function of the target instruction, comprising: instruction code analysis means for inputting the target and prefix instructions and analyzing the operational details of instruction code thereof; and instruction execution means for executing these instructions based on the operational details analyzed by the instruction code analysis means; the instruction code analysis means comprises immediate-data expansion means for expanding immediate data necessary for-the execution of the target instruction which is subjected to function expansion by the prefix instruction based on the prefix instruction; and the instruction execution means executes the target instruction based on immediate data expanded by the immediate-data expansion means.
The instruction code analysis means analyzes the input instruction codes and performs processing necessary for the execution of the instruction by the instruction execution means, such as calculating an address in the storage means for storing data that is manipulated by this instruction.
A target instruction and a prefix instruction that expands the function of that target instruction are input to the data processing circuit of this invention. The prefix instruction is not executed independently by the instruction execution means; its function is to expand the function of a subsequent target instruction when that instruction is executed.
The immediate-data expansion means expands the immediate data that is necessary for the execution of the target instruction, on the basis of the prefix instruction. This immediate data is the immediate data that will be necessary during the execution of the target instruction, such as immediate data comprised within the instruction code thereof or immediate data comprised within the instruction code of the prefix instruction.
In this case, the expansion of the immediate data could be ordinary zero extension or sign extension, a broadening of the bit width of the immediate data written in these instruction codes, or the addition of-certain bits thereto. In other words, this aspect of the invention makes it possible to expand immediate data by the addition of certain bits, as specified by a prefix instruction.
Thus it is possible to set the number of bits of the instruction code to be small, even when it includes immediate data that tends to increase the number of bits of instruction code. This enables an improvement in the efficiency with which memory is used, with a simple structure that uses shorter fixed-length instruction codes but without requiring complicated control circuitry that would otherwise be required for variable-length instruction codes.
The data processing circuit in accordance with a second aspect of this invention has an architecture such that fixed-length instruction codes are input and executed thereby.
The use of fixed-length instruction codes in this aspect of the invention makes it possible to shorten the time required for decoding the instructions, in comparison with processing involving instruction codes of a variable bit length, and also reduce the size of the data processing circuitry.
Since immediate data can be expanded by prefix instructions, the immediate data, which often tends to lengthen the instruction codes, can be made shorter. Since the size of the fixed-length instruction codes can therefore be reduced, unnecessarily verbose-parts of the instruction coding can be cut efficiently, enabling improvements in the efficiency with which memory is used, particularly in how instruction codes are stored in memory.
In the data processing circuit in accordance with a third aspect of this invention, the bit width of the fixed-length instruction codes is less than or equal to the bit width of data or addresses that can be processed by the data processing circuit.
Even when the bit width of the instruction codes is set to be less than the bit width of data or addresses that can be processed by the data processing circuit, this aspect of the invention makes it possible to expand immediate data to the bit width that can be processed by the data processing circuit. Since the bit width of the instruction codes can thus be set to less than the bit width of data or addresses that can be processed by the data processing circuit, the efficiency with which memory is used can be improved.
The data processing circuit in accordance with a fourth aspect of this invention is configured to input fixed-length instruction codes of a 16-bit width; the immediate-data expansion means expands the imm
Kubota Satoshi
Kudo Makoto
Miyayama Yoshiyuki
Donaghue Larry D.
Oliff & Berridg,e PLC
Seiko Epson Corporation
LandOfFree
Data processing circuit with target instruction and prefix... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Data processing circuit with target instruction and prefix..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data processing circuit with target instruction and prefix... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2614882