Electrical computers and digital processing systems: processing – Processing architecture – Superscalar
Reexamination Certificate
1997-05-20
2003-05-06
Zimmerman, Mark (Department: 2671)
Electrical computers and digital processing systems: processing
Processing architecture
Superscalar
C712S202000, C712S210000, C712S225000, C711S121000, C711S138000, C711S145000
Reexamination Certificate
active
06560692
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a data processing circuit, a microcomputer incorporating this data processing circuit, and electronic equipment that is constructed by using this microcomputer.
2. Description of Related Art
In the prior art, a RISC microcomputer that is capable of manipulating 32-bit data uses fixed-length instructions that are 32 bits wide. This is because the use of fixed-length instructions enables a reduction in the time required for decoding the instructions in comparison with the use of variable-length instructions, and it also makes it possible to reduce the size of the circuitry of the microcomputer.
However, even with a 32-bit microcomputer, it isn't always necessary to use the full 32 bits. Thus, if all of the instructions are written as 32-bit instructions, many of them will contain unused portions so that memory will be used inefficiently.
The present inventors have investigated the idea of a microcomputer that handles fixed-length instructions of a bit width that is narrower than that of the executable data, to improve the usage efficiency without making the control circuitry more complicated.
However, simply cutting 32-bit fixed-length instructions to fit into a fixed 16-bit length, for example, causes problems as described below.
An important feature of a RISC microcomputer is the use of general-purpose registers, whose contents have no pre-assigned meaning. For that reason, when a stack pointer is used, one of the general-purpose register is used as the stack pointer and an instruction that acts upon a general-purpose register is used to implement stack operation.
When coding a process that takes data specified by a memory address obtained by adding a predetermined offset to the stack pointer and transfers it to a predetermined register, using an instruction that acts upon a general-purpose register, for example, it is necessary to include within the object code of that instruction the offset, data specifying the predetermined register, and data specifying the register to be used as the stack pointer.
Thus, if an instruction that acts upon a general-purpose register is used when coding a process that acts upon the stack pointer, a large amount of data has to be specified in the object code, making it difficult to code the details of the instruction within a 16-bit fixed-length. Increasing the instruction length to 32 bits, for example, would result in a large number of instructions that do not particularly need the entire 32 bits, so that many instructions will contain unused portions, leading to a decrease in the efficiency with which memory is used.
In addition, increasing the instruction length will also increase the amount of memory required for storing such instructions, so it is preferable from the point of view of efficient use of memory to not only use fixed-length instructions, but also make the instructions as short as possible.
When a program is executed that was written in a language that secures a storage region for auto-variables linked to the stack pointer, such as programming language C, there are many instructions that act upon the stack pointer, so it is preferable to have efficient coding and execution of instructions that act upon the stack pointer.
In that case, it is therefore preferable to have an architecture that enables the coding and execution of instructions that are as short as possible, when executing a process that acts upon the stack pointer.
It has become common recently to incorporate general-purpose registers internally, particularly with a RISC CPU, to increase capabilities. Providing a large number of registers internally makes it possible for many processes to be executed rapidly within the CPU itself, without having to access memory. If such a large number of internal registers is provided, a large number of registers have to be saved during the process of register save and restoration when an interrupt is processed or a subroutine is called.
The description now turns to a prior-art example of instructions that save and restore the contents of registers, frequently used when entering and leaving a subroutine, even within stack-related instructions.
The instruction set of a microcomputer usually has instructions for saving and restoring the contents of registers in the CPU to and from a stack provided in memory. These are either dedicated instructions or instructions that address registers indirectly.
In the Intel 80386 chip, push, pusha, and pushad instructions are available for writing the contents of registers to the stack, and pop, popa, and popad instructions are available for returning data from the stack to registers.
When the contents of a register are written to the stack by the push instruction, the register has to be specified as an operand, such as ‘push EAX.’ This example concerns a 32-bit register EAX. If the contents of registers EAX, ECX, EDX, and EBX are all to be written to the stack, this push instruction must be repeated, as follows:
push EAX
push ECX
push EDX
push EBX
If such push and pop instructions are used for each of the registers, the size of the object code increases and a large number of program execution steps is required, leading to delays in the execution time or processing of the program.
That is why the pusha or pushad instruction is used to write the contents of all eight of the general-purpose registers of the 80386 to the stack. pusha operates on the lower 16 bits of each of the eight registers, and pushad operates on the entire 32 bits. The use of pusha and pushad can remove the need to repeat the push instruction eight times.
The pop, popa, and popad instructions act in a similar manner.
Disadvantages of repeating the push instruction include the increased length of program code and the delays in execution caused by executing a fetch for each instruction.
From this point of view, the pusha and pushad instructions provide a large improvement when writing the contents of all eight registers to the stack. However, this is not an advantage when writing fewer than the eight registers, such as four or six registers.
In other words, if the pusha, pushad, popa, and popad instructions of the 80386 operate upon all of the registers, instructions with delayed cycle lengths must be used when there is no need to save and restore the contents of all of the registers. In such a case, one instruction will suffice, but this gives rise to a problem in that the execution cycle of that instruction takes too long.
Similar saving and restoration of the program counter is necessary when program flow branches to a subroutine and returns from the called routine, using instructions such as the call instruction and ret instruction. With a RISC CPU of the prior art, these processes are implemented by software. In other words, the program counter is saved and restored by executing assembler instructions (object code) that declare these processes. This leads to an increase in object code of the call and ret instructions, and the execution of a fetch for each instruction makes the execution speed sluggish.
SUMMARY OF THE INVENTION
An objective of this invention is to provide a data processing circuit, microcomputer, and electronic equipment having an architecture that enables efficient coding of processes that act upon the stack pointer within a short instruction length, for execution.
Another objective of this invention is to provide a data processing circuit, microcomputer, and electronic equipment that enables efficient coding of processes that save and restore the contents of registers, with fast processing of interrupts and subroutine calls and returns.
In order to achieve the above objectives, a first aspect of this invention provides a data processing circuit comprising:
a dedicated stack pointer register that is used only for the stack pointer;
decoding means for decoding object code of a group of dedicated stack pointer instructions which have object code specifying the dedicated stack pointer register as an implicit operand and which rel
Kubota Satoshi
Kudo Makoto
Miyayama Yoshiyuki
Sato Hisao
Monestime Mackly
Oliff & Berridg,e PLC
Seiko Epson Corporation
Zimmerman Mark
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