Data processing circuit

Details Data processing circuit Data processing circuit

1994-12-09

1996-02-27

Mai, Tan V.

Boots, shoes, and leggings

G06F 738

Patent

active

054954339

ABSTRACT:
A data processing circuit being provided with a select and output circuit 5 selectively outputting an operation result of an arithmetic logic unit (ALU)4 to a D bus 8, a temporary latch 2 holding a data part of a register 11 into which the operation result is written, and a select and output circuit 3 selectively outputting the data held in the temporary latch 2 to the D bus 8, wherein the select and output circuit 5 for the ALU 4 outputs only bits corresponding to a designated writing size to the D bus 8, the select and output circuit 3 for the temporary latch 2 outputs other than bits corresponding to the designated writing size to the D bus 8, and the register 11 inputs and stores data from the D bus 8, thereby leading to be capable of reducing the area of the register file 1.

REFERENCES:
patent: 4525776 (1985-06-01), Eldumiati et al.
patent: 4740894 (1988-04-01), Lyon
patent: 4881168 (1989-11-01), Inagami et al.
patent: 5073864 (1991-12-01), Methvin et al.
patent: 5153846 (1992-10-01), Rao
patent: 5163154 (1992-11-01), Bournas et al.
patent: 5177701 (1993-01-01), Iwasa

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