Communications: electrical – Continuously variable indicating – With meter reading
Patent
1985-11-13
1989-01-24
Griffin, Robert L.
Communications: electrical
Continuously variable indicating
With meter reading
361413, 361416, 361395, H05K 336, G06F 100
Patent
active
048003832
DESCRIPTION:
BRIEF SUMMARY
This invention relates to data processor arrays and a method of producing them. In such an array a plurality of data processors are arranged to operate in parallel but also, very often, interacting so that the output data signals of each processor depend on the output data signals of others of the processors.
True array processors can consist of a large number of identical binary processors arranged logically in a two dimensional matrix array in such a way that interconnections can be provided between adjacent processors in the array. Each processor has an input supplied from its 4, 6 or 8 nearest neighbours. In a conventional processor the normal function is for a new piece of information extracted from the processor's memory to be combined in a logical or arithmetic operation with the data which is already held in the register or accumulator of the processor. The elements of an array processor will perform this function but, in addition, of the data to be combined, part may be output from one, or all, or some combination of the nearest neighbour processors.
In order to take full advantage of this type of processing structure it is useful for the array of processors to be as large as possible. To accomplish this a number of processors are assembled as a single integrated circuit, as many processors as possible on each one. These integrated circuits are then assembled on printed circuit boards, the printed circuit preferably being as large as possible to accommodate as many integrated circuits as possible.
Practical arrays, however, may well be of such a size as to involve a number of separate printed circuit boards, and this number may be quite large. For example, each array board may contain between 500 and 2000 processors or more, which means that there may well be several hundred, possibly more than 1000, interconnections between the adjacent boards in the array. This very large number of cnnections makes the array boards difficult to mount and expensive to interconnect, particularly if they are mounted in conventional racks and interconnected in the conventional way by means of a back plane. It should be noted that it is desirable that all array boards should be as nearly identical as possible to facilitate manufacture, maintenance etc.
One method commonly used to overcome situations where there are a number of interconnections is to multiplex these interconnections. This, however, reduces the speed at which such circuits can work. For instance if two signals are to be multiplexed down a single line, then the effective operating speed of the circuit may be halved, and so on. The great virtue of the parallel processor array is that all processors work individually at logic speeds, each complete operation being accomplished in a single clock cycle which may be typically half or quarter of a microsecond. Since any operation may involve communication with adjacent processors, the interconnections between the processors must provide the communicating signals at a speed compatible with that at which the processors operate, otherwise a degradation in the performance of the entire data processing system will be evident. It is, therefore, undesirable to use a multiplexing technique, if the array is to run at its maximum possible speed.
It is an object of the present invention to enable a large number of array boards to be interconnected in a simple manner, while providing fully parallel interconnection paths between the processors in the array. It should be noted that it is desirable to keep these interconnections short, since they carry high speed signals.
According to this invention there is provided a method of producing a data processor array, said method including the steps of notionally arranging, in a two dimensional matrix array, a plurality of sub-array boards each carrying a plurality of data processors comprising a respective sub-array of said matrix array, forming a stack with said sub-array boards in an order determined as if said array comprised a sheet folded along lines between the sub-array bo
REFERENCES:
patent: 4193086 (1980-03-01), Kawaguchi
patent: 4237546 (1980-12-01), Wells
I.E.E. Conference Publication No. 14, Institution Of Electrical Engineers Symposium On Applications of Microelectronics, Southampton, 21-23 Sep. 1965 (London, GB) pp. 19/1-19/12, see p. 19/8, line 50-p. 19/9, line 15.
Griffin Robert L.
Smith Ralph E.
Stonefield Systems Plc.
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