Data processing arrangement using an interconnecting network on

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G06F 1300

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active

048211761

ABSTRACT:
A data processing arrangement intended for use, inter alia, in a multi-processing system for use in association with a systolic array is implemented on a single semiconductor chip. The arrangement includes processing means (AU, MU) and storage means (ACC), interconnectable via an electronic equivalent (MM) of a cross-bar switch.

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patent: 4438492 (1984-03-01), Harmon, Jr. et al.
patent: 4460972 (1984-07-01), Homan et al.
patent: 4528625 (1985-07-01), McDonough et al.

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