Data processing arrangement including multiple groups of I/O dev

Details Data processing arrangement including multiple groups of I/O dev Data processing arrangement including multiple groups of I/O dev

1980-03-17

1982-05-25

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 946

Patent

active

043320112

ABSTRACT:
A data processing arrangement including a microprocessor and a plurality of input/output devices arranged in groups in accordance with a predetermined priority scheme. Each input/output device is capable of initiating a service request via an interrupt line to the microprocessor as a result of which a machine cycle is initiated by the microprocessor in which control signals are produced by the microprocessor and applied to logic circuitry coupled to the groups of input/output devices. The logic circuitry operates to propagate a low voltage level at the output of the input/output device initiating the service request down through the lower priority groups and to change inputs of the lower priority input/output devices from normal high voltage levels to low voltage levels. Data is then applied by the input/output device initiating the service request to the microprocessor, following which a microprocessor reset instruction resets the device. In accordance with the present invention, once a given input/output device has been pre-conditioned for resetting, the microprocessor and logic circuitry operate to prevent a change in this condition by preventing a low voltage level established at the output of another input/output device in a higher-priority group subsequently initiating a service request from being propagated to the input of the lower-priority input/output device.

REFERENCES:
patent: 3909790 (1975-09-01), Shapiro et al.
patent: 4009470 (1977-02-01), Danilenko et al.

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