Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2000-05-30
2003-07-22
Treat, William M. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C345S504000, C712S011000, C712S015000, C712S016000
Reexamination Certificate
active
06598146
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a data-processing arrangement comprising a plurality of elementary circuits such as processing and memory circuits. The invention may be applied in, for example, a video-processing arrangement for transforming video data from one to another display format.
BACKGROUND OF THE INVENTION
It is possible to process data in the following manner. A first processing circuit processes a block of data so as to obtain a once processed block of data, which is written into a memory circuit. Subsequently, a second data processor reads the once processed block of data, processes it so as to obtain a twice processed block of data which is written into the same or another memory circuit, and so on. That is, in effect, the data processing circuits form a data processing chain. Each processing circuit carries out a different element of the data-processing chain. The memory circuits provide buffer storage between two successive data processing circuits.
It is possible to provide each processing circuit with a program memory. The program memory will thus contain a set of instructions that cause the processing circuit to carry out the element of the data-processing chain concerned. The European Patent Application published under number 0 373 714 appears to disclose a data processor, which comprises a plurality of processor elements and a program memory for each processor element.
SUMMARY OF THE INVENTION
It is an object of the invention to allow relatively easy programming.
According to the invention, a data-processing arrangement, which comprises a plurality of elementary circuits such as processing and memory circuits, comprises a controller. The controller is programmed to successively apply, in response to a task-initialization data, control data to certain subsets of elementary circuits. This causes the data-processing arrangement to process a block of data in accordance with a certain data-processing chain. Each subset of elementary circuits implements a different element of the data-processing chain.
The invention takes the following aspects into consideration. In prior-art data-processing arrangement, several sets of instructions are required for programming the data-processing arrangement. Each set-is destined for a different processing circuit. Consequently, a software program for the prior-art data-processing arrangement will be relatively voluminous. Furthermore, the respective sets of instructions for the data processing circuits have to match because each element of the data processing chain has to match with its neighboring elements, if any. Consequently, it will be relatively complicated to write a software program for implementing a certain data processing chain. Programming will be even more complicated if the prior-art data-processing arrangement has to implement different data-processing chains because, for example, it has to process different types of data.
According to the invention, a task-initialization data defines a data-processing chain that is composed of several elements in terms of processing operations. The controller programs certain subsets of elementary circuits in response to the task-initialization data so that successively each subset carries out a different element of the data-processing chain. That is, the controller is programmed to appropriately program elementary circuits of the data-processing arrangement in response to a task-initialization data. Consequently, it is sufficient to apply a task-initialization data to the data-processing arrangement so as to cause the data-processing arrangement to process a block of data in a desired fashion. Consequently, the data-processing arrangement can be programmed simply by defining one or more data-processing chains in the form of task-initialization data. Consequently, the invention allows relatively easy programming.
REFERENCES:
patent: 5649135 (1997-07-01), Pechanek et al.
patent: 0780761 (1997-06-01), None
patent: 0780761 (1997-06-01), None
patent: 7152693 (1995-06-01), None
Andre DeHon, “Notes on Coupling Processors with Reconfigurable Logic”, Transit Note #118, MIT Artificial Intelligence Laboratory, Mar. 21, 1995.
Bru Bernard
Duranton Marc
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