Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2002-02-14
2010-12-21
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
Reexamination Certificate
active
07856543
ABSTRACT:
A data processing architecture comprising:an input device for receiving an incoming stream of data packets; anda plurality of processing elements which are operable to process data received thereby;wherein the input device is operable to distribute data packets in whole or in part to the processing elements in dependence upon the data processing bandwidth of the processing elements.
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Bond Jeff
Cameron Ken
Dejaegher Matthias
Faulds Gordon
Halamish Danny
Chan Eddie P
Glenn Michael A.
Glenn Patent Group
Rambus Inc.
Vicary Keith
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