Data processing architectures for packet handling using a...

Electrical computers and digital processing systems: processing – Processing architecture – Array processor

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C712S036000

Reexamination Certificate

active

07917727

ABSTRACT:
An input/output system transfers data packets to and from a SIMD array of processing elements (PEs) such that different sizes of data packets are transferred to respective ones of the PEs. The packets are transferred in batches to respective different addresses in the array under the control of the PEs. Transfer to or from the array may be carried out when either a batch or part of a batch is ready for transfer. The decision to transfer either full or part batches is made in dependence upon the speed of the PEs and the speed and intermittency of the data packets.

REFERENCES:
patent: 4755986 (1988-07-01), Hirata
patent: 5224100 (1993-06-01), Lee et al.
patent: 5325493 (1994-06-01), Herrell et al.
patent: 5418970 (1995-05-01), Gifford
patent: 5420858 (1995-05-01), Marshall et al.
patent: 5440550 (1995-08-01), Follett
patent: 5603028 (1997-02-01), Kitsuregawa et al.
patent: 5768275 (1998-06-01), Lincoln et al.
patent: 5781549 (1998-07-01), Dai
patent: 6047304 (2000-04-01), Ladwig et al.
patent: 6081523 (2000-06-01), Merchant et al.
patent: 6088355 (2000-07-01), Mills et al.
patent: 6094715 (2000-07-01), Wilkinson et al.
patent: 6147996 (2000-11-01), Laor et al.
patent: 6389018 (2002-05-01), Clauberg
patent: 6393026 (2002-05-01), Irwin
patent: 6631422 (2003-10-01), Althaus et al.
patent: 6735219 (2004-05-01), Clauberg
patent: 6831923 (2004-12-01), Laor et al.
patent: 6832261 (2004-12-01), Westbrook et al.
patent: 6836479 (2004-12-01), Sakamoto et al.
patent: 6907001 (2005-06-01), Nakayama et al.
patent: 6963572 (2005-11-01), Carr et al.
patent: 7016367 (2006-03-01), Dyckerhoff et al.
patent: 7317730 (2008-01-01), Devanagondi et al.
patent: 7349389 (2008-03-01), Nie
patent: 7620050 (2009-11-01), Kawashima et al.
patent: 7656799 (2010-02-01), Samuels et al.
patent: 2001/0018732 (2001-08-01), Nakagoshi et al.
patent: 2002/0003795 (2002-01-01), Oskouy et al.
patent: 2002/0075882 (2002-06-01), Donis et al.
patent: 2002/0122424 (2002-09-01), Kawarai et al.
patent: 2003/0074388 (2003-04-01), Pham et al.
patent: 2003/0231627 (2003-12-01), John et al.
patent: 2004/0017807 (2004-01-01), Dorr et al.
patent: 2005/0027793 (2005-02-01), Hass
patent: 2005/0243829 (2005-11-01), Spencer
patent: 2010/0086233 (2010-04-01), Kitashou
patent: 2010/0165991 (2010-07-01), Veal et al.
patent: 0992895 (2000-04-01), None
patent: 2001177574 (2001-06-01), None
patent: 92/15960 (1992-09-01), None
patent: 00/30322 (2000-05-01), None
“Router Architectures Exploiting Input-Queued, Cell-Based Switching Fabrics”; M. Ajmone Marsan and A. Bianco and P. Giaccone and E. Leonardi and F. Neri; Aug. 17, 2000.
WO 97/29613 “Parallel on-the-fly Processing of Fixed Length Cells” Clauberg; Published Aug. 14, 1997.
“Input Queued Switches” Cell Switching vs. Packet Switching; Ganjali, Yasharl; Keshavarzian, Abtin; Shah, Devavrat; 2003.
Rai et al. (Packet Processing on a SIMD Stream Processor); Network Processor Design, vol. 3: Issues and Practices, vol. 3 (The Morgan Kaufmann Series in Computer Architecture and Design); Morgan Kaufmann (Feb. 15, 2005); 26 pages.
Seshadri et al. (A Case for Vector Network Processors); Proceedings of the Network Processors Conference West, Oct. 2002, 19 pages.
Wolf et al. (Design Issues for High-Performance Active Routers); This paper appears in: Selected Areas in Communications, IEEE Journal on ; Issue Date: Mar. 2001 ; vol. 19 Issue:3 ; on pp. 404-409.
Search Report issued in connection with UK Application No. GB 0203634.1 dated Aug. 12, 2002.
Great Britain Search Report, dated May 23, 2005, in connection with GB Patent Application No. GB0506813.5.
Great Britain Search Report, dated May 23, 2005, in connection with GB Patent Application No. GB0506818.4.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Data processing architectures for packet handling using a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data processing architectures for packet handling using a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data processing architectures for packet handling using a... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2756514

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.