Data processing apparatus with serial and parallel priority

Details Data processing apparatus with serial and parallel priority Data processing apparatus with serial and parallel priority

1979-10-10

1982-04-20

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 1516

Patent

active

043262503

ABSTRACT:
A combined serial priority and parallel priority apparatus and method of operation for use in data processing systems. Each of the parallel priority circuits are interconnected by a common parallel priority bus which carries parallel priority signals indicating the priority level of any unit requesting access. If a unit requesting access has a lower priority than indicated on the parallel priority bus, that requesting unit is inhibited from obtaining access. If a requesting unit has higher priority than the signals on the parallel priority bus, that unit in turn causes the priortiy bus to be switched to the higher priority level.
The serial priority circuits act together with other serial priority circuits within a group of priority circuits set to the same parallel priority. In this configuration, the parallel priority circuits perform a high-order priority determination while the serial priority circuits perform a low-order priority determination. A unit requesting access will be granted access only when its parallel priority is equal to or greater than the parallel priority signal on the parallel priority bus and only when its serial priority is greater than any other unit commonly connected in the serial priority configuration.

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