Data processing apparatus with improved bit masking capability

Details Data processing apparatus with improved bit masking capability Data processing apparatus with improved bit masking capability

1989-07-31

1991-10-08

Herndon, Heather R.

Boots, shoes, and leggings

340798, G06F 1520

Patent

active

050560417

ABSTRACT:
A graphics processor device is disclosed which performs bit-by-bit masking outside of the central processing unit, by way of a read-modify-write cycle to external or internal memory. A mask bus is incorporated into the device so that, for each bit of the external data word, a mask bit is present which indicates whether data from the central processing unit (CPU) is to be written to memory (unmasked) or if that bit of memory contents is to remain unaltered (masked). The CPU data is written into a latch at the memory interface during such time as the latch is isolated from the external memory bus and during the read portion of the read-modify-write cycle. For those bits which are to be masked, the latch is overwritten with the data read from memory, while for the unmasked bits the latch remains isolated from the external memory bus. During the write portion of the read-modify-write cycle, the contents of the latch are driven onto the external memory bus. The bit-by-bit masking may also be done for data in internal memory, by multiplexing the CPU data and the internal memory data onto the CPU data bus.

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patent: 4562537 (1985-12-01), Barnett et al.
patent: 4779223 (1988-10-01), Asal et al.
NEC Electronics U.S.A., Inc. 1982 Catalog, Microcomputer Division, pp. 515-536 .mu.PD7220/GDC Graphics Display Controller.

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