Data processing apparatus registers

Details Data processing apparatus registers Data processing apparatus registers

1996-10-08

1999-10-19

Ngo, Chuong Dinh

Boots, shoes, and leggings

36473603, G06F 738

Patent

active

059699752

ABSTRACT:
A data processing system is provided including an arithmetic logic unit 20, 22, 24 receiving input operands from M X-bit registers to produce output data words stored within N Y-bit registers, where M/N=3, 8.ltoreq.Y-X.ltoreq.16 and 3X=2Y. This arrangement is particularly suited for digital signal processing and in situations where each input operand is used a plurality of times before a new input operand is loaded in its place in a register.

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Kiyohara, Tokuzo et al., Register Connection: A New Approach to Adding Registers into Instruction Set Architectures, Computer Architecture News, vol. 21, No. 2, May 1, 1993, pp. 247-256.
Lee, Ruby B., "Subword Parallelism with MAX-2", IEEE Micro, vol. 16, No. 4, Aug. 1, 1996, pp. 51-59.
Muller, Mike, "ARM6 a High Performance Low Power Consumption Macrocell", Proceedings of the Spring Computer Society International Conference (COMPCON), No. Conf. 38, Feb. 22, 1993, Institute of Electrical and Electronics Engineers, pp. 80-87.
Sarkar, S. et al., "DSP Coprocessor for Event Filtering in a Data Acquisition System", 1990 IEEE Nuclear Science Symposium Conference Record, vol. 1 of 2, Oct. 22-27, 1990, pp. 313-317.

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