Data processing apparatus providing cyclic addressing of a data

Details Data processing apparatus providing cyclic addressing of a data Data processing apparatus providing cyclic addressing of a data

1988-02-03

1988-11-22

Harkcom, Gary V.

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36472416, 36472419, 375 14, G11C 700, G11C 2100

Patent

active

047870656

ABSTRACT:
A data processing apparatus in which a memory (10) is accessed at addresses stored in an address regiser (20). An incrementation circuit (38) successively increments or decrements the address stored in the principal register, under the control of an address cycling circuit (22). A pair of auxiliary registers (30, 35) respectively store the minimum and maximum address values to be reached in the principal register, and a comparison circuit (37) determines when the address therein matches the minimum or maximum value. The address cycling circuit, together with the comparison circuit, loads the principal register with the minimum address value when the address therein reaches the maximum value, the address therein thereafter being decremented, and loads it with the maximum address value when the address therein reaches the minimum value, the address therein thereafter being incremented. Such operation is particularly useful for preforming the functions of a fixed or adaptive transversal filter for data transmission, the data stored in the memory being the filter coefficients.

REFERENCES:
patent: 3141151 (1964-07-01), Gilson
patent: 4016543 (1977-04-01), Franks
patent: 4241416 (1980-12-01), Tarczy-Hornoch
patent: 4280199 (1981-07-01), Osakabe et al.
patent: 4422175 (1983-12-01), Bingham et al.
patent: 4462074 (1984-07-01), Linde
patent: 4628532 (1986-12-01), Stone et al.
patent: 4638457 (1987-01-01), Schrenk

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