Data processing apparatus providing autoloading of memory pointe

Details Data processing apparatus providing autoloading of memory pointe Data processing apparatus providing autoloading of memory pointe

1978-12-29

1981-02-10

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 934

Patent

active

042505453

ABSTRACT:
A Central Processing Unit (CPU) provides programmable autoloading of memory pointer registers. The CPU includes an op-code extension register (OER) to store a code specifying the autoloading status of each memory pointer register. Whether or not a particular memory pointer register is loaded at the end of an instruction cycle with an operand address carried by the current instruction depends on the binary state of a particular bit position in the OER corresponding to the particular memory pointer register. The contents of the OER can be changed by means of an instruction for transferring a new code to OER. A CPU architecture having an OER permits software specification of autoloading without significantly increasing the number of op-codes required to define the instruction set. Fewer op-codes generally permit shorter instructions. The advantages provided by shorter instructions are reduced memory overhead for program storage and increased processing efficiency in data processing systems having a small word size.

REFERENCES:
patent: 3292151 (1966-12-01), Barnes et al.
patent: 3331056 (1967-07-01), Lethin et al.
patent: 3764988 (1973-10-01), Onishi
patent: 4037211 (1977-07-01), Ikuta
patent: 4095278 (1978-06-01), Kihara
MCS 6500 Microcomputer Family Hardware Manual, MOS Technology, Inc., 950 Rittenhouse Road, Norristown, Pa., Jan. 1976, pp. 29-31.
MCS 6500 Microcomputer Family Programming Manual, MOS Technology, Inc., 950 Rittenhouse Road, Norristown, Pa., Jan. 1976, pp. 23-30.

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