Data-processing apparatus provided with a finite-state machine t

Details Data-processing apparatus provided with a finite-state machine t Data-processing apparatus provided with a finite-state machine t

1986-10-01

1988-08-02

Chan, Eddie P.

Boots, shoes, and leggings

G06F 0930

Patent

active

047617349

ABSTRACT:
A data-processing apparatus having a processor, a read-write memory, a data bus, a program counter, a program memory and an instruction register. There is also a feedback finite-state machine possessing a multibit-wide output whose bits are determined in at least two successive machine cycles. This output is connected to a comparator which has its other input connected to the instruction register. A certain equality condition can invalidate the current instruction so that the latter acts as a rapidly performable dummy (NOP) instruction and a program jump can be performed. In a further expansion another multibit-wide output of the finite-state machine can be coupled to the data bus via a decoding circuit.

REFERENCES:
patent: 4351050 (1982-09-01), Higashiyana
patent: 4554630 (1985-11-01), Sargent et al.
patent: 4689738 (1987-08-01), Van Wijk et al.

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