Electrical computers and digital processing systems: processing – Instruction decoding – Predecoding of instruction component
Reexamination Certificate
2001-05-16
2008-03-18
Pan, Daniel (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction decoding
Predecoding of instruction component
C712S219000
Reexamination Certificate
active
07346760
ABSTRACT:
When fetching an instruction from a plurality of memory banks, a first pipeline cycle corresponding to selection of a memory bank and a second pipeline cycle corresponding to instruction readout are generated to carry out a pipeline process. Only the selected memory bank can be precharged to allow reduction of power consumption. Since the first and second pipeline cycles are effected in parallel, the throughput of the instruction memory can be improved.
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Sato Hisakazu
Yamada Akira
Yoshida Toyohiko
Pan Daniel
Renesas Technology Corp.
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