Data processing apparatus having op-code extension register

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G06F 1300

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active

042939070

ABSTRACT:
A Central Processing Unit (CPU) includes a hardware op-code extending register (OER) for storing a code for programmable selection of optional CPU features which modify processor operations defined by the op-code in each instruction. A control section in the CPU decodes both the op-code of a current instruction and the code in the OER, effectively combining the two to form an extended op-code capable of defining a larger set of processor operations than the op-code carried in each instruction. The code in the OER is changed only when the CPU executes an instruction for transferring a new code into OER. Thus the code in OER can remain stationary over many instruction cycles.

REFERENCES:
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MOS Technology, Inc., MCS6500 Microcomputer Family Hardware Manual, 1976.
J. Dirac, Call Instruction, May 1966, IBM Tech. Disc. Bull., vol. 8, No. 12, p. 1751.

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