Data processing apparatus having a parallel arrangement of data

Details Data processing apparatus having a parallel arrangement of data Data processing apparatus having a parallel arrangement of data

1990-10-31

1992-08-11

Shaw, Gareth D.

Boots, shoes, and leggings

395800, 364DIG1, 3642283, 3642291, 3642319, 3642436, G06F 1580, G06F 1300

Patent

active

051387042

ABSTRACT:
A control method for processing elements (PE) in a parallel processing system, such as an array processor, in which data processing is carried out with data transfer between the PEs, and wherein the data transfer between the PEs is performed simultaneously with the data operations in the PEs to improve the processing speed of the parallel processing system. Three buffer memories are respectively connected to a data input path from one data procesing apparatus, a data output path to another data processing apparatus, and data paths for transmitting data from or to the data operation unit in the data processing apparatus itself having these three buffer memories. Connections between these buffer memories and the data paths are switched, in such a manner that one of these buffer memories is connected to the external data input path from one data processing apparatus, while the other two buffer memories, are connected to the data output path to another data processing apparatus and the data paths from or to the data operation unit, respectively. When receiving data in the buffer memory connected to the data input path from one data processing apparatus, the buffer memory connected to the data output path transmits data to another data processing apparatus, and the buffer memory connected to the data paths from or to the data operation unit sends data to this unit and receives the operation results from this unit.

REFERENCES:
patent: 4303988 (1981-12-01), Tsuboka et al.
patent: 4314333 (1982-02-01), Shibayama et al.
patent: 4504909 (1985-03-01), Acharya et al.
patent: 4546431 (1985-08-01), Horvath

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