Data processing apparatus having a clock control unit for decrea

Details Data processing apparatus having a clock control unit for decrea Data processing apparatus having a clock control unit for decrea

1997-01-30

1998-12-15

Butler, Dennis M.

395309, G06F 104

Patent

active

058505415

ABSTRACT:
In a CPU comprising a CPU section and a BCU section, the processing speed of the CPU section is prevented from decreasing, the amount of power consumed by the CPU section is reduced, and the need of a wait control function in the CPU section is eliminated. A clock control section 105c distributes an externally supplied clock 111 to the inside of a CPU section 101 and a BCU section 105. During a read access request from the CPU section 101 to a storage device 106, the period of a CPU clock 112 supplied to the CPU section 101 is extended. That is, the state immediately before the change point of the CPU clock 112 when the CPU section 101 inputs input data via an internal data bus 104 is extended until read data has been established on the internal data bus 104.

REFERENCES:
patent: 5151986 (1992-09-01), Langan et al.
patent: 5155812 (1992-10-01), Ehlig et al.
patent: 5201036 (1993-04-01), Yoshimatsu
patent: 5371880 (1994-12-01), Bhattacharya
patent: 5448744 (1995-09-01), Eifert et al.
patent: 5452434 (1995-09-01), MacDonald

Affiliated with

Also associated with

Rating

Data processing apparatus having a clock control unit for decrea does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data processing apparatus having a clock control unit for decrea, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data processing apparatus having a clock control unit for decrea will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1464488